ASIC(SPGP)
SM 6-13
G144/G145
Detailed
Des
cription
s
6.4 ASIC(SPGP)
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ARM946ES
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32-bit RISC embedded processor core
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6KB instruction cache and 16KB data cache
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No tightly coupled memory
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Memory protection unit & CP15 control program
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Dual bus architecture for bus traffic distribution
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AMBA high performance bus (AHB)
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System bus with SDRAM
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IEEE1284 compliant parallel port interface
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Printer video controller for LBP engines
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Graphic execution unit for banding support of printer languages
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Printer video controller for LBP engines
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PVC : Printer video controller without RET algorithm
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HPVC : Printer video controller with RET algorithm. (Line Memory & Lookup
Table Memory : 512 x 8 , 4096 x 16)
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Engine controller
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Motor control unit
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Motor speed lookup table memory (128 x 16 x 2)
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Pulse width modulation unit
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4 channels are supported
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ADC Interface unit
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3 ADC channels are available
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ADC core (ADC8MUX8) maximum clock frequency :3 MHz
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USB 2.0 interface
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Package: 272 pins PBGA
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Power : 1.8V(Core), 3.3V(IO) power operation
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Speed : 166MHz core (ARM946ES) operation, 60MHz bus operation
6.4.1 MEMORY
This machine has flash ROM and DRAM memory units. There are 2-SODIMM
sockets to allow for extra DRAM or Flash ROM (Postscript Option) being added.
6.4.2 FLASH MEMORY
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Record/download system program from the PC Interface
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Fax for journal list
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Memory for one touch dial
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Speed dial list:
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Size : 2M Byte
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Access Time : 70 nsec
Summary of Contents for Aficio BP20N
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