SMIQ
Digital Standard 3GPP W-CDMA (FDD)
1125.5555.03
E-9
2.171
2.14.1.1 System
Components
Scrambling Code Init
Channelization Code
Generator
Channelization Code
Number
Data Source
Slot and Frame Builder
Data Offset
Demultiplexer
Scrambling Unit
CH
SCi
SCq
Ci
Cq
Si
Sq
Power Control
Channel Power
Summation
Filtering
Ch. 0
Ch. N
Uplink Modifier ("HPSK")
SCq'
Di
Dq
Scrambling Code
Generator I
Scrambling Code Init
Scrambling Code
Generator Q
Fig. 2-97
Components of 3GPP W-CDMA transmission system
The individual functional blocks are described below in detail.
Scrambling code generator
The scrambling code generator (formerly long code generator) is used to scramble the chip sequence
as a function of the transmitter. The structure and initialization rule of the generator differ depending on
the link direction and the mode (long or short).
1. Downlink scrambling code generator
This generator consists of a pair of shift registers from which the binary sequences for in-phase and
quadrature components of the scrambling code are determined. Fig. 2-98 shows that the I component
results from an EXOR link of the LSB outputs whereas for the Q component the register contents are
first output masked and then EXORed.
Note
:
As an alternative, the Q component can be determined via a second pair of registers with
the same structure, which idle for a certain number of cycles before the scrambling code
bits are output. This I/Q offset is 131.072 in the downlink and 16.777.232 in the similarly
designed uplink long scrambling code generator. For reasons of simplicity, the
implementation shown in Fig. 2-98 is the better choice.
Generator polynomials of downlink scrambling code generators
Shift register 1
x
18
+x
7
+1
Shift register 2
x
18
+x
10
+x
7
+x
5
+1
