Rohm BU2365FV Technical Notes Download

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●

Recommended Operating Range

Parameter Symbol

Limit

Unit

Supply voltage

VDD

3.0

～

3.6

Ｖ

Input H voltage

VINH

0.8VDD

～

VDD

Ｖ

Input L voltage

VINL

0.0

～

0.2VDD

Ｖ

Operating temperature

Topr

－

～

℃

Output load

22Pin / 19Pin CL_CLK768FS/384FS

32(MAX)

13Pin , 14Pin

CL_BUFOUT

50(MAX)

18Pin / 24Pin

CL_CLK512FS/54M

15(MAX)

●

Electrical characteristics
VDD=3.3V, Ta=25

℃

, Crystal frequency (XTAL_IN)

27.000000MHz, at no load, unless otherwise specified.

Parameter Symbol

Limit

Unit Condition

Min. Typ. Max.

【

Consumption circuit current

】

IDD

－

55 71.5

At no output loads

【

Output H voltage

】

VOH 2.4

－

When current load

-4.0mA

【

Output L voltage

】

VOL

－

0.4

When current load

4.0mA

【

Pull-Up resistance value

】

FSEL

、

Pull-Up

168 260 578

Specified by a current value running

when a voltage of 0V is applied to a

measuring pin. (R

DD/I)

【

Pull-Down resistance value

】

TEST

Pull-down

31 48 106

Specified by a current value running

when a VDD is applied to a measuring

pin. (R

VDD/I)

【

Output frequency

】

CLK768FS

：

FSEL=L CLK768

FS_L

－

33.868800

－

MHz

XTAL_IN

(3136/625)/4

CLK768FS

：

FSEL=H CLK768

FS_H

－

36.864000

－

MHz

XTAL_IN

(2048/375)/4

CLK384FS CLK384

－

18.432000

－

MHz

XTAL_IN

(2048/375)/8

CLK512FS CLK512

－

24.576000

－

MHz

XTAL_IN

(2048/375)/6

CLK54M

－

54.000000

－

MHz

XTAL_IN

(32/4)/4

【

Output waveform

】

Duty

Duty1 45

％

Measured at a voltage of 1/2 of VDD

Rise time

－

2.5

－

nsec

Period of time required for the output

to reach 80% from 20% of VDD

Fall time

－

2.5

－

nsec

Period of time required for the output

to reach 20% from 80% of VDD

【

Jitter

】

Period-Jitter

P-J1

－

psec

※

Period-Jitter

MIN-MAX P-J

MIN-MAX

－

300

－

psec

※

【

Output Lock-Time

】

Tlock

－

msec

※

【

Frequency stability

】

F/F0

－

ppm

-10

～

℃ 、

VDD=3.3V

0.15V

※

【

Frequency sensitivity

】

F/Fc

60 ppm

※

【

Frequency sensitivity linearity

】

Linearity

－

10 10

ppm

※

【

Buffer skew

】

Tskew

_BUF

－

500

－

500

psec

Phase difference between
BUF_OUT1 and BUF_OUT2



【

Buffer delay

】

Td_BUF

－

4 8

nsec

Phase difference between
BUF_IN and BUF_OUT

Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTAL_IN.

Summary of Contents for BU2365FV

Page 1: ...oviding the reduced number of the system components Features 1 The ROHM s unique PLL technology allows for the generation of high C N clocks 2 Built in high precision VCXO which is essential for the DVD recorder system 3 Built in buffer having high driving force Load capacity output CL 50pF 27MHz drive 1 input 2 outputs 4 Built in half pulse clock protection HPC 5 Built in power down function Icc ...

Page 2: ...d to a measuring pin R VDD I Output frequency CLK768FS FSEL L CLK768 FS_L 33 868800 MHz XTAL_IN 3136 625 4 CLK768FS FSEL H CLK768 FS_H 36 864000 MHz XTAL_IN 2048 375 4 CLK384FS CLK384 FS 18 432000 MHz XTAL_IN 2048 375 8 CLK512FS CLK512 FS 24 576000 MHz XTAL_IN 2048 375 6 CLK54M CLK54M 54 000000 MHz XTAL_IN 32 4 4 Output waveform Duty Duty1 45 50 55 Measured at a voltage of 1 2 of VDD Rise time Tr ...

Page 3: ...system in use 5 Frequency sensitivity Frequency sensitivity linearity These parameters represents that the frequency falls within the area shown in Fig 2 in the control circuit of control voltage shown in Fig 1 It shows the value of IC itself Since no consideration is given to the stability of the crystal oscillator it should be separately studied according to the system in use Common Recommended ...

Page 4: ... 12 24 576MHz output waveform VDD 3 3V CL 15pF Fig 13 24 576MHz Period Jitter VDD 3 3V CL 15pF Fig 14 24 576MHz spectrum VDD 3 3V CL 15pF Fig 3 33 8688MHz output waveform VDD 3 3V CL 32pF Fig 4 33 8688MHz Period Jitter VDD 3 3V CL 32pF 1 0V div 5 0nsec div 1 0V div 500psec div 10dB div 10KHz div RBW 1KHz VBW 100Hz 1 0V div 5 0nsec div 1 0V div 500psec div 10dB div 10KHz div RBW 1KHz VBW 100Hz 1 0V...

Page 5: ... 50pF Fig 21 VCXO_OUT 27MHz output waveform VDD 3 3V CL 4pF Fig 22 VCXO_OUT 27MHz Period Jitter VDD 3 3V CL 4pF Fig 24 Buffer skew output waveform VDD 3 3V CL 50pF Fig 25 Buffer delay IN OUT1 VDD 3 3V CL 50pF Fig 26 Buffer delay IN OUT2 VDD 3 3V CL 50pF 1 0V div 5 0nsec div 1 0V div 500psec div 10dB div 10KHz div RBW 1KHz VBW 100Hz 1 0V div 5 0nsec div 1 0V div 500psec div 10dB div 10KHz div RBW 1...

Page 6: ...0 25 50 75 100 Temperature T Fall Time Tf nsec VDD 2 9V VDD 3 3V VDD 3 7V 0 10 20 30 40 50 60 70 80 90 100 25 0 25 50 75 100 Temperature T Period Jitter 1 σ P J1 σ psec 0 100 200 300 400 500 600 25 0 25 50 75 100 Temperature T Period Jitter MIN MAX P JMIN MAX psec VDD 2 9V VDD 3 3V VDD 3 7V 45 46 47 48 49 50 51 52 53 54 55 25 0 25 50 75 100 Temperature T Duty Duty VDD 3 7V VDD 2 9V VDD 3 3V VDD 2 ...

Page 7: ... Temperature Period Jitter MIN MAX Fig 43 24 576MHz Temperature rise time Fig 44 24 576MHz Temperature fall time Fig 45 24 576MHz Temperature Period Jitter 1σ VDD 3 3V VDD 2 9V VDD 3 7V VDD 2 9V VDD 3 3V VDD 3 7V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 25 0 25 50 75 100 Temperature T Fall Time Tf nsec VDD 2 9V VDD 3 3V VDD 3 7V 0 10 20 30 40 50 60 70 80 90 100 25 0 25 50 75 100 Temperature T Period Jitter...

Page 8: ... MIN MAX Fig 52 27MHz BUFFER Temperature Duty Fig 53 27MHz BUFFER Temperature rise time Fig 54 27MHz BUFFER Temperature fall time VDD 2 9V VDD 3 3V VDD 3 7V VDD 2 9V VDD 3 3V VDD 3 7V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 25 0 25 50 75 100 Temperature T Fall Time Tf nsec VDD 2 9V VDD 3 3V VDD 3 7V 0 10 20 30 40 50 60 70 80 90 100 25 0 25 50 75 100 Temperature T Period Jitter 1 σ P J1 σ psec 0 100 200 30...

Page 9: ...r MIN MAX Fig 64 27MHz VCXO Control voltage Frequency data Fig 66 Power down Standby Current 45 46 47 48 49 50 51 52 53 54 55 25 0 25 50 75 100 Temperature T Duty Duty VDD 2 9V VDD 3 3V VDD 3 7V 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 25 0 25 50 75 100 Temperature T Rise Time Tr nsec VDD 2 9V VDD 3 3V VDD 3 7V VDD 2 9V VDD 3 3V VDD 3 7V 15 12 9 6 3 0 3 6 9 12 15 25 0 25 50 75 100 Temperature T Center freq...

Page 10: ...Jitter MIN MAX 0 100 200 300 400 500 600 700 0 10 20 30 40 50 60 70 Output Load CL pF Period Jitter MIN MAX P JMIN MAX psec VDD 3 3V 0 100 200 300 400 500 600 700 0 10 20 30 40 50 60 70 Output Load CL pF Period Jitter MIN MAX P JMIN MAX psec VDD 3 3V 0 100 200 300 400 500 600 700 0 10 20 30 40 50 60 70 Output Load CL pF Period Jitter MIN MAX P JMIN MAX psec VDD 3 3V 0 100 200 300 400 500 600 700 0...

Page 11: ...84FS 18 432MHz output 20 VSS GND for PLL Logic 21 VDD Power supply for PLL Logic 22 CLK768FS FSEL L 33 8688 MHz output FSEL OPEN 36 864 MHz output 23 OE Output enable pin L POWER DOWN OPEN NORMAL equipped with pull up resistor 24 CLK54M 54MHz output 22 CLK768FS 21 VDD 20 VSS 19 CLK384FS 18 CLK512FS 17 VDD_B 1 VDD54M 2 VSS54M 3 FSEL 4 TEST 5 AVDD 6 AVSS 7 XTAL_IN 23 OE 8 XTAL_OUT 24 CLK54M 16 BUF_I...

Page 12: ...in the measurements on the tests before shipment MIN TYP MAX True value nsec 17 0 20 0 23 0 2 Half pulse clock protection HPC The CLK768FS output is provided with a function used to prevent the occurrence of asynchronous droop of half cycle or less i e half pulse clock while in frequency selection under the FSEL pin control This function is designed to set the frequency to output L fixed after the...

Page 13: ...rcuit of I O PIN No Equivalent circuit of I O 3 23 With pull up 4 With pull down 13 14 18 19 22 24 10 7 16 8 B U 2 3 6 5 F V Lot No Fig 81 To the inside of IC From the inside of IC To the inside of IC To the inside of IC To the inside of IC From the inside of IC ...

Page 14: ... for the use of the BU2365FV the operating margin should be thoroughly checked 6 Depending on the conditions of the substrate mount an additional electrolytic capacitor between the power supply and GND terminal 7 For EMI protection it is effective to put ferrite beads in the origin of power supply to be fed to the BU2365FV from the substrate or to insert a capacitor of 1Ω or less impedance which b...

Page 15: ...oneous mounting can break down the ICs Furthermore if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal the ICs can break down 7 Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them 8 Inspection with set PCB On the inspection with the set PCB...

Page 16: ...of feed Embossed carrier tape 2000pcs E2 The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand Reel Direction of feed 1pin 1234 1234 1234 1234 1234 1234 1234 1234 When you order please order in times the amount of package quantity B U 2 3 6 5 E F Type Packing specification E2 Reel like emboss taping 2 Part No Packa...

Page 17: ...ll bear no re sponsibility whatsoever for any dispute arising from the use of such technical information The Products specified in this document are intended to be used with general use electronic equipment or devices such as audio visual equipment office automation equipment communication devices elec tronic appliances and amusement devices The Products are not designed to be radiation tolerant W...

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