2-13
UA
RT
_
R
X
UA
RT
_
T
X
CY
2_
T
C
K
CY
2_
T
D
I
CY
2_
T
MS
SERIALIZATION & DEBUG CONNECTOR
SPI Serial Flash
CY
2_
N
C
E
CY
2_
T
D
O
NM
RE
S
FPGA Configuration Interface
F2
5M
CL
K2
5
_
F
P
GA
Main 25 MHz Clock
CL
K2
5
_
P
H
Y
CY
2_
T
C
K
CY
2_
T
DI
CY
2_
T
M
S
CY
2_
T
DO
SP
I_D
SP
I_C
L
K
SP
I_N
C
S
SP
I_Q
S
D
R_
CL
K
C
LK
2
5_
FPG
A
CY
2_
CO
NF
_
D
O
N
E
C
Y
2
_
NS
TA
TU
S
FP
GA
Co
nf
igur
at
ion M
o
de
: A
ct
ive
ser
ial
via
SP
I
SP
I_D
SP
I_C
L
K
SP
I_N
C
S
C
Y
2
_
NC
O
N
FI
G
CY
2_
RE
CO
NF
IG
CY
2
_
N
CE
NM
RE
S
CY
2_
RE
CO
NF
IG
VC
C3
VC
C
3
VC
C3
VC
C3
VC
C3
GM
II
_R
X_
CLK
VC
C3
VC
C
3
SP
I_D
SP
I_Q
SP
I_C
L
K
SP
I_N
C
S
SP
I_Q
G
M
II_
GT
X_
CL
K
BU
TT
ON
NM
AX
RE
S
IN
TP
CY
2_
T
MS
CY
2_
T
D
O
CY
2_
T
C
K
CY
2_
T
D
I
CL
KU
SR /
IO
F1
5
nD
EV
_C
LR
/ IO
J15
DA
TA
0
/
IO
H2
CO
NF
_
D
O
N
E
H1
4
nS
TA
TU
S
F4
nC
O
N
FI
G
H5
DC
LK
H1
C
o
nf
ig
urat
io
n
TM
S
J5
TC
K
H3
TD
I
H4
TD
O
J4
nC
E
J3
nC
E
O
/ IO
F1
6
DA
TA
1
, AS
D
O /
I
O
C1
FL
_n
CE
, nC
SO /
IO
D2
IN
IT_
D
O
N
E
/ IO
G1
6
MS
EL
1
H1
2
MS
EL
0
H1
3
DE
V_
O
E
/
I
O
J16
CR
C_
ERRO
R /
I
O
G1
5
JT
AG
MS
EL
2
G1
2
IC
44A
E
P3C
10
F256
N
Cl
o
ck
p
or
ts
CL
K1
3
/
I
R9
CL
K1
2
/
I
T9
CL
K1
5
/
I
R8
CL
K1
4
/
I
T8
Ba
nk
4
CL
K9
/
I
B9
CL
K8
/
I
A9
CL
K1
1
/
I
B8
CL
K1
0
/
I
A8
Ba
nk
7
CL
K5
/
I
E1
6
GN
D /
I
E1
5
PL
L
4
_O
UT
p / IO
P1
4
PL
L
4
_O
UT
n / IO
R1
4
PL
L
2
_O
UT
p / IO
B1
4
PL
L
2
_O
UT
n / IO
A1
4
CL
K7
/
I
M1
6
CL
K6
/
I
M1
5
Ba
nk
7
CL
K1
/
I
E1
CL
K0
/
I
E2
PL
L
3
_O
UT
p / IO
D3
PL
L
3
_O
UT
n / IO
C3
PL
L
1
_O
UT
p / IO
R4
PL
L
1
_O
UT
n / IO
T4
CL
K3
/
I
M1
CL
K2
/
I
M2
Ba
nk
5
Ba
nk
2
Ba
nk
8
Ba
nk
3
Ba
nk
6
Ba
nk
8
Ba
nk
1
Ba
nk
3
Ba
nk
4
3C
5, 3C
10
3C
16
, 3
C
2
5
IO
IO
IO
IO
PL
L
1
PL
L
1
PL
L
2
PL
L
2
I
I
I
I
I
I
I
I
CL
K
CL
K
CL
K
CL
K
CL
K
CL
K
CL
K
CL
K
IC
44G
EP
3
C
1
0
F
2
5
6
N
UA
RT
_T
X
UA
RT
_R
X
VC
C2
.5
J4
1: 1-
2 & J4
2: 2-
3 =>
fa
st
P
O
R
(3-
9
m
s)
J4
1: 2-
3 & J4
2: 1-
2 =>
norm
al P
O
R
(50-
200m
s)
VC
C3
LE
D_
1
RB
_N
IR
Q
RB
_N
RES
/D
R
EQ
0
/C
C
S
4
/W
W
R
C
L
K
1
20_4
RB
_C
K
IOB
GM
II
_M
TX
_C
LK
NA
[0
..
2
5
]
NA
9
DI
A
G
5
V
TP
2
2
R
227
1.
5K
1
2
4
3
D9
RB
48
1
K
DR
AK
0
3.
3V
1
NC
3
MR
5
NC
7
S_
TX
9
S_
RX
11
BO
OT
SRC
13
GN
D
15
SE
_S
W_
CS
2
SE
_B
O
OT
_
C
S
4
SE
_D
6
SE
_Q
8
SE
_C
L
K
10
NC
12
NC
14
NC
16
3.
3V
/S
E_
HO
LD
/M
R
+5
V
S_
TX
S_
RX
BO
OT
SRC
GN
D
JT
AG
_T
DO
/S
E_
CS
SE
_D
SE
_Q
SE
_C
L
K
JT
AG
_T
DI
JT
AG
_
T
C
K
JT
AG
_T
MS
si
ce
r
B
si
ce
r
BN
io
s2
si
gna
l
na
m
es
&
de
rec
ti
ons
r
el
ate
to
he
ad
er m
ou
nte
d on pr
int
se
rver
P
C
B
ST
1
PS
-16
P
E
-D4T
1
-B
1E
HO
LD
1
VC
C
2
NC
3
CS
7
Q
8
WP
9
VS
S
10
D
15
SC
L
K
16
NC
4
NC
5
NC
6
NC
11
NC
12
NC
13
NC
14
IC
51
M
2
5P
32
CY2
_
[T
M
S
..T
D
I.
.T
CK
..
T
D
O]
R
229
10
K
R2
3
0
10
K
R2
3
1
1
0
K
R2
0
0
10K
R2
3
5
1
0
K
R2
3
6
1
0
K
R2
3
7
1
0
K
R2
3
8
1
0
K
R2
3
9
1
0
K
R2
4
1
1
0
K
R2
4
2
1
0
K
R2
4
3
1
0
K
TP
2
3
TP
2
4
R
232
1.
5K
CB
25
CE
0.
1u
CB24
CE
0.
1u
CB
26
CE
0
.1u
No
M
o
u
n
t
R
226
R2
3
3
4
9
.9
1
%
R2
3
4
4
9
.9
1
%
IN
H
1
GN
D
2
OU
T
3
VC
C
4
Y2
SG
-71
0
EC
K
-25M
-B
1
2
3
4
8
7
6
5
RA
88
EX
BV
8V
1
03
JV
SP
I_[
C
L
K..Q.
.D..
N
CS
]
VC
C
DA
CK
0
RB
_S
PA
RE
R2
4
0
1.5K
R2
2
8
2
2
R1
7
5
2
2
R1
7
8
2
2
R2
7
3
2
2
MS
EL
2
MS
EL
1
/W
W
R
S
D
R_
CL
K
RB
_N
RES
RB
_N
IR
Q
NM
AX
RE
S
LE
D_
1
IN
TP
GM
II
_R
X_
CLK
GM
II
_M
TX
_C
LK
NA
[0
..
2
5
]
IO
C1
4
IO
F8
VR
EF
B7
N0
C1
1
IO
A1
0
VR
EF
B8
N0
C6
IO
D1
4
IO
D1
1
IO
A1
2
IO
B1
2
IO
B1
0
IO
C9
IO
D9
IO
E9
IO
C8
IO
A7
IO
B7
IO
B1
1
IO
E1
1
IO
D1
2
IO
A6
IO
B6
IO
E1
0
IO
A1
1
Ba
nk
7
Ba
nk
8
IO
D8
IO
E8
IO
A1
5
IO
F9
IO
A1
3
IO
B1
3
Ba
nk
7
+
8
IO
D6
IO
A4
IO
B5
IO
E7
IO
E6
IO
A5
IO
B3
IO
D5
IO
B4
IO
A2
IO
A3
VR
EF
(
3
C
1
6
o
n
ly
)
VR
EF
(
3
C
1
6
o
n
ly
)
IC
44E
E
P
3C
10F256
N
NA
3
NA
5
NA
2
NA
4
DA
CK
0
RB
_N
IR
Q
RB
_N
RES
RB_S
EN
S
E
_A
RB_S
EN
S
E
_B
ND
3
1
ND
3
0
ND
2
9
ND
2
8
ND
2
7
ND
2
6
ND
2
5
ND
2
4
ND
1
5
ND
1
4
ND
1
3
ND
1
2
ND
1
1
ND
1
0
ND
9
ND
8
RB_N
BS
ND
2
3
ND
2
2
ND
2
1
ND
2
0
ND
1
9
ND
1
8
ND
1
7
ND
1
6
ND
7
ND
6
ND
5
ND
4
ND
3
ND
2
ND
1
ND
0
RB_N
RDY
RB_N
RDY
RB_N
RES
RB_N
BS
VC
C3
Pull up/down to inactive levels
ROBI interface at FPGA
NA
[0
..
2
5
]
TP
2
5
NA
[0
..
2
5
]
R2
4
4
0
No
M
o
u
n
t
R2
7
8
R3
0
5
1
0
K
R3
1
4
1
0
K
R3
2
0
1
0
K
R3
5
0
1
0
K
R3
6
2
1
0
K
R3
7
2
1
0
K
R3
7
6
1
0
K
R3
2
1
1
0
K
N
D
[0
..31]
N
D[
0..31]
TP
2
6
RB
_N
BS
No
M
o
u
n
t
R3
1
8
No
M
o
u
n
t
R3
4
7
No
M
o
u
n
t
R2
8
0
/C
C
S
4
RB
_N
IR
Q
RB
_N
RES
DR
AK
0
DA
CK
0
RB_NI
RQ
DA
CK
0
/D
R
E
Q
0
/W
W
R
MAIN BOARD_Circuit Diagram 9/9
Summary of Contents for VS-300
Page 49: ...2 4 MAIN BOARD_Arrangement Diagram Soldering Side ...
Page 60: ...2 15 SERVO BOARD_Arrangement Diagram Soldering Side ...
Page 65: ...2 20 2 4 CARRIAGE BOARD CARRIAGE BOARD_Arrangement Diagram Component Side ...
Page 68: ...2 23 2 5 SUB BOARD SUB BOARD_Arrangement Diagram Component Side ...