RTD Embedded Technologies, Inc.
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44
DM35418HR/DM35218HR
User’s Manual
BDM-610010041 Rev F
ORDER -3 dB Cutoff
0
n/a
1
0.114791 * f
s
2
0.045995 * f
s
3
0.021236 * f
s
4
0.010255 * f
s
5
0.005042 * f
s
6
0.002501 * f
s
7
0.001246 * f
s
6.4.18
CH_INT_STAT(R
EAD
/C
LEAR
)
This is the status register for the channel interrupts. Reading a value of ‘1’ indicates that an event has occurred. Reading a value of ‘0’ indicates
that the event has not occurred. Writing a ‘1’ will clear that bit.
B0: ‘1’ = Low Threshold has been crossed
B1: ‘1’ = High Threshold has been crossed
6.4.19
CH_INT_ENA
(R
EAD
/W
RITE
)
This is the interrupts enable for the threshold detection. Bit defines are above. An interrupt is generated (if not already generated) each time a
sample is taken and the value is above the high threshold or below the low threshold.
6.4.20
CH_THRESH_LOW
(R
EAD
/W
RITE
)
Signed 32-bit value indicating the low threshold. If the input signal drops below this value, an interrupt or clock can be generated until the signal
goes above this value. The 3 least significant bits are ignored from the actual threshold value.
NOTE: The threshold value should not exceed the ADC range. If the
threshold value exceeds the ADC range unexpected results will occur.
6.4.21
CH_THRESH_HIGH
(R
EAD
/W
RITE
)
Signed 32-bit value indicating the high threshold. If the input signal goes above this value, an interrupt or clock can be generated until the signal
goes below this value. The 3 least significant bits are ignored from the actual threshold value.
NOTE: The threshold value should not exceed the ADC range. If the
threshold value exceeds the ADC range unexpected results will occur.
6.4.22
CH_LAST_SAMPLE
(R
EAD
-O
NLY
)
The last sample read from the ADC Converter, after filtering. This is the same value that is written to the DMA FIFO.
