RTD Embedded Technologies, Inc.
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31
DM35418HR/DM35218HR
User’s Manual
BDM-610010041 Rev F
5.4.3.3. Single Ended, Unipolar, 0-10V Full-scale range
The following figure shows an example how to set up the FPGA registers for a single-ended, unipolar signal with a gain of 1. Also provided are
graphs showing the difference between the input vs. output from the PGA.
Figure 12: Unipolar Single Ended Example
5.4.3.4. Differential, Unipolar, 0-10V Full-scale range
The following figure shows an example how to set up the FPGA registers for a differential, unipolar signal with a gain of 1. Also provided are
graphs showing the difference between the input vs. output from the PGA.
Figure 13: Unipolar Differential Example
+
-
VREF
CHn_Front_End_Config
[PGA_A[1:0]]
G=1
:
0, 0
+15V
-15V
IN+
IN-
A1 A0 -> G
Gain
CHn_Front_End_Config
[BIP_UNI]
VREF: -5V: [BIP_UNI] = 1
X
+
-
CHn_Front_End_Config
[VREF_NORMAL] = 1
CHn_Front_End_Config
[SE_DIFF] = 0
V
in
V
PGA
t
10V
V
in
(t)
V
PGA
(t)
t
5V
-5V
5V
+
-
VREF
CHn_Front_End_Config
[PGA_A[1:0]]
G=1
:
0, 0
+15V
-15V
IN+
IN-
A1 A0 -> G
Gain
CHn_Front_End_Config
[BIP_UNI]
VREF: -5V: [BIP_UNI] = 1
+
-
CHn_Front_End_Config
[VREF_NORMAL] = 1
CHn_Front_End_Config
[SE_DIFF] = 1
V
in
V
PGA
External Ground Reference Resistor
t
10V
V
in
(t)
V
PGA
(t)
t
5V
-5V
5V
