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37
DM35418HR/DM35218HR
User’s Manual
BDM-610010041 Rev F
6.2
BAR2: Functional Block Standard DMA
This section describes a standard DMA engine implementation that may be used by the Functional Blocks. Any Functional Block that uses DMA
shall use this implementation so that the kernel mode driver may be used to service it, resulting in better performance.
Table 20: DMA Registers
Offset
0x03
0x02
0x01
0x00
D + 0x00
FB_DMAm_Stat_Underflow
FB_DMAm_Stat_Overflow
FB_DMAm_Setup
FB_DMAm_Action
D + 0x04
FB_DMAm_Current_Buffer
FB_DMAm_Count
D + 0x08
FB_DMAm_RD_FIFO_CNT
FB_DMAm_WR_FIFO_CNT
D + 0x0C
FB_DMAm_Last_Action
FB_DMAm_Stat_Complete
FB_DMAm_Stat_Invalid FB_DMAm_Stat_Used
D + 0x10
FB_DMAm_CTRL0
FB_DMAm_STAT0
Reserved
D + 0x14
Reserved
FB_DMAm_SIZE0
D + 0x18
FB_DMAm_ADDRESS0
D + 0x1C
D + 0x20
FB_DMAm_CTRL1
FB_DMAm_STAT1
Reserved
D + 0x24
Reserved
FB_DMAm_SIZE1
D + 0x28
FB_DMAm_ADDRESS1
D + 0x2C
…
D + 0x10 +
(0x10 * n)
FB_DMAm_CTRLn
FB_DMAm_STATn
Reserved
D + 0x14 +
(0x10 * n)
Reserved
FB_DMAm_SIZEn
D + 0x18 +
(0x10 * n)
FB_DMAm_ADDRESSn
D + 0x1C +
(0x10 * n)
6.2.1
FB_DMA
M
_A
CTION
(R
EAD
/W
RITE
)
After writing to the Action register, the driver should poll the Last_Action register (below) until it reads the same value. This shows that the
action has been performed by the DMA state machine. This is especially important when entering and exiting the Clear state.
0x00 = Clear: Clear the Current Buffer field, the internal offset counters, and the FIFO. DMA is stopped.
0x01 = Go: Starts DMA
0x02 = Pause: DMA transfers are stopped, but all internal registers maintain their state. During PAUSE you will still receive
Stat_Underflow and Stat_Overflow interrupts. After PAUSE, you may transition to GO or CLEAR.
0x03 = Halt: Buffer has been filled that has the HALT bit set, or has attempted to use a buffer with the
bit cleared. After HALT,
you must transition to CLEAR.
6.2.2
FB_DMA
M
_L
AST
_A
CTION
(R
EAD
/W
RITE
)
The DMA Engine writes the value of FB_DMAm_Action to this register after it has completed this channel. This indicates to the driver that the
last command has been processed. It specifically aids the transition to Clear. When transitioning to Clear, the driver should wait until
FB_DMAm_Last_Action indicates that the Clear has been processed before allowing any other Action changes.
The driver may also write a value to this register and then poll the register to see when the value changes. This method can be used to detect
when the DMA engine services the channel without an Action change.
6.2.3
FB_DMA
M
_S
ETUP
(R
EAD
/W
RITE
)
B0:IntEna: Set to ‘1’ to enable the DMA engine to generate interrupts on completion of a buffer.
B1:ErrIntEna: Set to ‘1’ to enable the DMA engine to generate interrupts on error.
B2:Direction (RO or R/W): Set to ‘1’ to transfer from the FPGA to the PCI bus. Clear to ‘0’ to transfer from the PCI bus to the
FPGA.
B3:IgnoreUsed: Set to ‘1’ to prevent an error condition when accessing a buffer with the
bit set. When "IgnoreUsed" is set, the
hardware will still set the Used_Desc bit (below) if the next buffer has the Used bit set. However, it will not generate an interrupt, and
will not PAUSE the DMA engine. Examples are continuous output from a DAC, or very large Pre-trigger buffering using system
memory.
