FP5/GP5 User’s Manual 65
Chapter 3 - Programming Features
FP5/GP5 Operation
Phase Loss Protection
· Input Phase Loss Detection (n083, In Ph Loss Lvl)
The input phase loss detection circuit monitors the DC bus current ripple
and activates when one of the input phases are lost. The detection circuit
calculates the maximum and minimum values of the DC bus voltage in
1.28 second intervals, and compares the difference (
∆
V) between these
values with the input phase loss detection level (n083). If
∆
V
≥
n083,
then input phase loss is detected; and after the input phase loss detection
delay time (fixed at approximately 10 seconds), an SPI fault occurs, and
the motor coasts to stop.
Input phase loss detection is disabled in the following cases:
· Parameter n083 is set to “100%”
· A Stop command is input
· Input magnetic contactor (MC) shuts OFF
· CPU A/D converter fault (CPF5)
· During deceleration
· Output current
≤
30% of Inverter rated current
No. Name Description
Factory
Default
n083 Input phase loss detection level Unit: 1%
Setting range: 1 to 100% of input voltage
7%
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