No.
Port
Port
Description
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
O
I
O
O
O
O
-
O
O
I
I
I
I
DB6
DB5
DB4
DB3
DB2
DB1
C1F1
C1F2
C2F1
C2F2
C2FL
/PBCK
DVSS2
FSDW
ULKFS
/JIT
C4M
C16M
/WE
/CS
XTALSEL
TEST0
CDROM
SRAM
TEST1
EFMI
ADATAI
/ISTAT
TRCNT
LOCK
PBFR
SMEF
SMON
DVDD2
SMDP
SMSD
BCKI
TESTV
DSPEED
LRCHI
SARM data I/O port 6
SARM data I/O port 5
SARM data I/O port 4
SARM data I/O port 3
SARM data I/O port 2
SARM data I/O port 1 (LSB)
Monitoring output for C1 error correction (RA1)
Monitoring output for C1 error correction (RA2)
Monitoring output for C2 error correction (RA3)
Monitoring output for C21 error correction (RA4)
C2 decoder flag (RA5, “H” : When the processing C2 code is impossible
correction status.)
Output of VCO/2 (4.3218MHz) (RA6)
Digital ground2
Window or unprotected frame sync (RA7)
Frame sync protection state (RA8)
Display of either RAM overflow or underflow for ±4 frame jitter margin
(RA9)
Only monitoring signal (4.2336MHz) (RA10)
16.9344MHz signal output (RA11)
Terminal for test
Terminal for test
Mode Selection1 (H: 33.8688MHz, L:16.9344MHz)
TEST input terminal (GND connection)
Mode Selection2 (H: CD-ROM, L: CDP)
TEST input terminal (GND connection)
TEST input terminal (GND connection)
EFM signal input
Serial audio data input of 48 bit/Slot (MSB first)
The internal status output
Tracking counter input signal
Output signal of LKFS condition sampled PBFR/16 (if LKFS is “H”, LOCK
is “H”, if LKFS is sampled “L” at least 8 times by PBFR/16, LOCK is “L”)
Write frame clock (Lock: 7.35KHz)
LPF time constant control of the spindle servo error signal
ON/OFF control signal for spindle servo
Digital VDD2
Spindle Motor drive (Rough control in the SPEED mode, Phase control
in the PHASE mode)
Spindle Motor drive (Velocity control in the PHASE mode)
Audio data bit clock input of 48 bit/Slot (2.1168MHz)
TEST input terminal (GND connection)
TEST input terminal (VDD connection)
Channel clock input of 48 bit/Slot (44.1KHz)
Block Diagrams
9-14
Samsung Electronics
Summary of Contents for MAX-805
Page 2: ...ELECTRONICS Samsung Electronics Co Ltd Feb 1998 Printed in Korea Code no AH68 20181A ...
Page 8: ...Remote Control ...
Page 50: ...Samsung Electronics 9 3 TDA7265 AIC1 9 3 1 Main 9 3 IC TR Internal Diagrams Block Diagrams ...
Page 62: ...10 PCB Diagrams 10 1 Main Samsung Electronics 10 1 ...
Page 63: ...10 2 Front PCB Diagrams 10 2 Samsung Electronics ...
Page 64: ...10 3 CD PCB Diagrams 10 3 1 Main Samsung Electronics 10 3 ...
Page 65: ...PCB Diagrams 10 3 3 SUB 10 4 Samsung Electronics ...
Page 68: ...12 2 Front Schematic Diagrams 12 2 Samsung Elctronics UIC1 LC866224 ...
