S3C80A5B
BASIC TIMER AND TIMER 0
10-5
TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)
The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match
interrupt (T0INT). T0OVF is interrupt level IRQ0, vector FAH. T0INT also belongs to interrupt level IRQ0, but is
assigned the separate vector address, FCH.
A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. The
T0INT pending condition must, however, be cleared by the application’s interrupt service routine by writing a "0" to
the T0CON.0 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the T0
reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH) and
clears the counter.
If, for example, you write the value ‘10H’ to T0DATA and ‘0BH’ to T0CON, the counter will increment until it reaches
‘10H’. At this point, the T0 interrupt request is generated, the counter value is reset, and counting resumes. With
each match, the level of the signal at the timer 0 output pin is inverted (see Figure 10-3).
Interrupt
Enable/Disable
(T0CON.1)
Pending
(T0CON.0)
CTL
P2.0
T0CON.5
T0CON.4
Match Signal
T0CON.3
IRQ0(INT)
R (Clear)
CLK
Match
Data Register
Buffer Register
Comparator
Counter
Figure 10-3. Simplified Timer 0 Function Diagram: Interval Timer Mode
