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2. SGH-X430 Circuit Description
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Since the play data of YMU762MA3 are interpreted at anytime through FIFO,
the length of the data(playing period) is not limited, so the device can
flexiblysupport application such as incoming call melody music distribution
service. The hardware sequencer built in this device allows playing of the
complex music without giving excessive load to the CPU of the portable
telephones. Moreover, the registers of the FM synthesizer can be operated
directly for real time sound generation, allowing, for example, utilization of
various sound effects when using the game software installed in the portable
telephone.
YMU762 includes a speaker amplifier with high ripple removal rate whose
maximum output is 550mW (SPVDD=3.6V). The device is also equipped with
conventional function including a vibartor and a circuit for controlling LEDs
synchornous with music.
For the headphone, it is provided with a stereophonic output terminal.
For the purpose of enabling YMU762MA3 to demonstarte its full capablities,
Yamaha purpose to use "SMAF:Synthetic music Mobile Application Format" as a
data distribution format that is compatible wiht multimedia. Since the SMAF
takes a structure that sets importance on the synchronization between sound
and images, various contents can be written into it including incoming call
melody with words that can be used for traning karaoke, and commercial
channel that combines texts, images and sounds, and others. The hardware
sequencer of YMU762MA3 directly interprets and plays blocks relevant to
systhesis (playing music and reproducing ADPCM with FM synthesizer) that are
included in data distributed in SMAF.
5) Memory
This system uses SHARP's
memory, LRS1828.
It is consisted of 128M bits flash memory and 32M bits SCRAM. It has 16 bit
data line, D[0~15] which is connected to trident, LCD or CSP1093. It has 22
bit address lines, A[1~22]. They are connected too. CP_CSROMEN and
CO_CSROM2EN signals, chip select signals in the trident enable two memories.
They use 3 volt supply voltage, VCCD.
During wrting process, CP_WEN is low and it enables writing process to flash
memory and SCRAM. During reading process, CP_OEN is low and it output
information which is located at the address from the trident in the flash
memory or SCRAM to data lines. Each chip select signals in the trident select
memory among 2 flash memory and SCRAM. Reading or writing procedure is
processed after CP_WEN or CP_OEN is enabled. Memories use FLASH_RESET,
which is buffered signal of RESET from PSC2106, for ESD protection. A[0]
signal enables lower byte of SCRAM and UPPER_BYTE signal enables higher
byte of SCRAM.
