MultiMediaCard Product Manual
SanDisk MultiMediaCard Product Manual Rev. 2 © 2000 SANDISK CORPORATION
58
<----- Host Command ----->
<-N
CR
Cycles ->
<-------- Response --------->
CMD
S T
Content
CRC E Z Z
P * * *
P S T
Content
CRC E
<-------- N
AC
Cycles ------->
<- Read Data
DAT
Z Z Z
* * * *
Z Z Z Z Z Z P
* * * * * * * * * *
P S D D D * * *
Figure 5-10 Transfer of Single Block Read
Data transmission from the card starts after the access time delay NAC beginning from the end bit of
the read command. After the last data bit, the CRC check bits are suffixed to allow the host to check
for transmission errors.
Multiple Block Read
—In multiple block read mode, the card sends a continuous flow of data blocks
following the initial host read command. The data flow is terminated by a stop transmission command
(CMD12). Figure 5-11 describes the timing of the data blocks and Figure 5-12 the response to a stop
command. The data transmission stops two clock cycles after the end bit of the stop command.
Figure 5-11 Timing of Multiple Block Read Command
<----- Host command -----> <-NCR
cycles ->
<-------- Response --------->
CMD
S T
content
CRC E Z Z P * * * P S T
content
CRC E
DAT
D D D * * * * * * * * D D D E Z Z * * * * * * * * * * * * * * * * * * * *
Figure 5-12 Timing of Stop Command (CMD12, Data Transfer Mode)
Stream Read
—The data transfer starts N
AC
clock cycles after the end bit of the host command. The bus
transaction is identical to that of a read block command (see Figure 5-10). As the data transfer is not
block oriented, the data stream does not include the CRC checksum. Consequently, the host can not
check for data validity. The data stream is terminated by a stop command. The corresponding bus
transaction is identical to the stop command for the multiple read block (see Figure 5-12).
5.10.3
Data Write
Single Block Write
—The host selects one card for
a data write operation by CMD7.
The host sets the valid block length for block
oriented data transfer (a stream write mode is
also available) by CMD16.
The basic bus timing for a write operation is given
in Figure 5-13. The sequence starts with a single
block write command (CMD24) which determines
(in the argument field) the start address. It is
responded by the card on the CMD line as usual.
The data transfer from the host starts N
WR
clock
cycles after the card response was received.
The data is suffixed with CRC check bits to allow
the card to check it for transmission errors. The
card sends back the CRC check result as a CRC
status token on the data line. In the case of
transmission error the card sends a negative CRC
status (‘101’). In the case of non erroneous
transmission the card sends a positive CRC status
(‘010’) and starts the data programming
procedure.
