COMe-cVR6 – User Guide Rev. 1.5
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2.3.6.3.
LVDS
LVDS is implemented by NXP PTN3460 eDP to LVDS bridge chip:
Input: Two eDP Lanes from CPU.
Output: Dual Channel LVDS to COMe connector.
Table 18: LVDS Bridge
COMe Connector
PTN3460
Description
LVDS_A*
LVS*O
Pin order according to COMe spec
LVDS_B*
LVS*E
LVDS_I2C_CK
-
connected to I2C_INT module bus
LVDS_I2C_DAT
-
connected to I2C_INT module bus
LVDS_VDD_EN
PVCCEN
LVDS_BKLT_EN
BKLTEN
LVDS_BKLT_CTRL
-
connected to EDP_BKLTCTL at SoC
2.3.6.4.
eDP
eDP is only available as option which bypasses the eDP2LVDS bridge.
Table 19: eDP
COMe Connector
SoC
Description
LVDS_A_CK
DP3_TX3
LVDS_A2
DP3_TX0
LVDS_A1
DP3_TX1
LVDS_A0
DP3_TX2
LVDS_I2C_CK
DP3_AUXN
LVDS_I2C_DAT
DP3_AUXP
EDP_HPD
DP3_HPD_SOC
LVDS_VDD_EN
EDP_VDD_EN_1V8
passed through FPGA/EC
LVDS_BKLT_EN
EDP_VDD_EN_1V8
passed through FPGA/EC
LVDS_BKLT_CTRL
EDP_BKLT_CTRL_1V8
passed through FPGA/EC
2.3.6.5.
VGA
VGA is implemented by Chrontel CH7517 DisplayPort to VGA bridge chip:
Input: two DisplayPort Lanes from CPU DDI3.
Output: VGA Video + VGA DDC
2.3.7.
Audio
The HD Audio (HDA) stream can be supported simultaneously on HDMI/DP.
Table 20: Audio
COMe Connector
SoC
Description
HDA_RST#
HDA_RST_1V8#
Passed through Levelshifter TXB0108
