COMe-cVR6 – User Guide Rev. 1.5
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COMe Signal
SoC Pin
Description
SPI_POWER
-
connected to V_3V3_S5
BIOS_DIS0#
input to control SPI_CS# logic
BIOS_DIS1#
input to control SPI_CS# logic
COMe-cVR6 supports on-module and off-module boot from SPI. For additional safety, a second on-module SPI flash
can be populated on the board. This also requires an adoption of the FPGA/EC code.
Table 29: External BIOS ROM Support: On-module and Off-module boot from SPI
BIOS_
DIS1#
BIOS_
DIS0#
MODULE_
CS#
COME_CS#
BIOS
entry
Description
1
1
SPI0_CS0#
‘1’
Module
1
0
SPI0_CS0#
‘1’
(Module)
Not Supported, was FWH, works
as module SPI
0
1
SPI0_CS1#
SPI0_CS0#
Carrier
0
0
SPI0_CS0#
SPI0_CS1#
Module
2.3.16.
Speaker Out (SPKR)
Table 30: Speaker Out (SPKR)
COMe Signal
SoC Pin
Description
SPKR
SPKR/AGPIO90
Speaker/Buzzer out
2.3.17.
Watchdog Timeout (WDT)
Table 31: Watchdog Timeout (WDT)
COMe Signal
SoC Pin
Description
WDT
po_wdt_o
Generated from kCPLD VHDL block
2.3.18.
Hardware Monitor (HWM)
Chip Nuvoton NCT7802Y, SM-Bus Adress: 5C.
Table 32: HWM
HWM Pin
Function
Description
VCORE
V_BAT
Measured with impedance converter, and G3
Isolation to prevent leakage in OPAMP
VSEN1
SoC Temp
Via external NTC resistor placed close to SoC
VREF
VREF output
Used for External NTC resistor (VSEN1)
VSEN2
COMe VCC (V_IN_VAR)
Voltage divider defined in schematics
VSEN3
COMe 5VSB (V_IN_5V0_S5)
Voltage divider defined in schematics
FANIN1
TACH_IN
From onboard FAN connector
FANCTL1
V_FAN
Controls output voltage of onboard FAN
connector via CPLD
