Block Diagram
Pin Descriptions
Symbol Name
Description
CLk
System Clock
Active on the positive going edge to sample all inputs
CS
Chip Select
Disables or Enables device operation by masking or enabling
all inputs except CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE Clock
Enable
CKE should be enabled at least one clock + tss prior to new
command.
Disable input buffers for power down in standby.
A0~A10/AP Address Row/Column addresses are multiplexed on the same pins.
Row address: RA0 ~ RA10, Column address: CA0 ~ CA7
BA Bank
Select
Address
Selects bank to be activated during row address latch time.
Selects band for read/write during column address latch time.
RAS
Row address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK
with CAS low. Enables column access.
WE
Write Enable
Enables write operation and Row precharge.
L(U)DQM
Data Input/Output Mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DW0-15
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power
Supply/Ground Power Supply: +3.3V±0.3V/Ground
VDDQ/VSSQ
Data Output
Power/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
NC/RFU No
Connection
- 27 -
Summary of Contents for DVD1451U
Page 1: ...GB SERVICE MANUAL DVD1451U MPEG4 PLAYER SERVICE MANUAL ...
Page 9: ... Pinout Diagram 8 ...
Page 10: ...PIN DESCRIPTON 9 ...
Page 11: ... 10 ...
Page 12: ... 11 ...
Page 13: ... 12 ...
Page 14: ... 13 ...
Page 15: ... 14 ...
Page 16: ... 15 ...
Page 17: ... 16 ...
Page 18: ... 17 ...
Page 19: ... 18 ...
Page 20: ... 19 ...
Page 21: ... 20 ...
Page 22: ... 21 ...
Page 25: ... 24 ...
Page 27: ...Pin Configuration 26 ...
Page 33: ... 32 6 Disassembly and Reassembly ...
Page 35: ... 34 8 Block Diagram ...
Page 39: ......