– 4 –
Fig. 1-3. IC901 Block Diagram
3. IC901 (V Driver)
A V driver (IC901) is necessary in order to generate the clocks
(vertical transfer clock and electronic shutter clock) which
driver the CCD.
In addition the XV1-XV13 signals which are output from IC101
are vertical transfer clocks, and the XSG signal is superim-
posed onto XV1, XV3 and XV5 at IC901 in order to generate
a ternary pulse. In addition, the XSUB signal which is output
from IC101 is used as the sweep pulse for the electronic shut-
ter.
Fig. 1-4. IC905 Block Diagram
4. IC905 (H Driver, CDS, AGC and A/D converter)
IC905 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
H1, H2, H3, H4, HL and RG are generated inside, and output
to CCD.
The video signal which is output from the CCD is input to pin
(25) of IC905. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the VGA (VGA: Variable Gain Amplifier). It is con-
verted internally into a small-amplitude actuating signal
(LVDS), and is then input to IC101. The gain of the VGA am-
plifier is controlled by pins (32), (33) and (34) using serial
signals which is output from IC101.
1
3
32
33
31
30
37
38
35
36
34
42
43
44
39
40
41
4
26
13
14
12
11
SUBCNT
VDC
CH1
V1
V6
V4
V5R
V5L
V3R
V3L
V1S
CH5
V5
CH3
CH4
V3
CH2
GND
VH
OV3B
OV3A
OV5B
OV5A
Level
conversion
29
V2
2 SUB
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
Level
conversion
28
RESET
20
OV1
8
VM
21
OV6
23
OV4
24
OV2
27
VL
10
OSUB
9
VMSUB
5
VL
2-level
2-level
2-level
3-level
25
19
17
15
18
VM
OV1S
OV3L
OV3R
OV5L
7
16 OV5R
VHH
6 VH
2-level
2-level
2-level
2-level
2-level
3-level
3-level
3-level
3-level
3-level
CCDIN
HL
H1 TO H4
HD
SDATA
SCK
SL
REFB
REFT
PRECISION
TIMING
GENERATOR
SYNC
GENERATOR
VGA
12-BIT
ADC
6~42 dB
VREF
CLAMP
INTERNAL
REGISTERS
INTERNAL
CLOCKS
CDS
HORIZONTAL
DRIVERS
4
AD9971
-3, 0, +3, +6dB
VD
CLI
RG
GP01
3V INPUT
1.8V OUTPUT
LDO
REG
GP02
TCLKP
REDUCED
RANGE
LVDS
OUTPUT
TCLKN
DOUT0P
DOUT0N
DOUT1P
DOUT1N