−
3
−
1A 1
1Y 2
2A 3
2Y 4
3A 5
3Y 6
GND 7
4Y
8
4A
9
5Y
10
5A
11
6Y
12
6A
13
V
CC
14
Fig. 1-3. IC902 Block Diagram
Fig. 1-4. IC907 Block Diagram
3. IC902 (H Driver) and IC907 (V Driver)
An H driver (IC902) and V driver (IC907) are necessary in
order to generate the clocks (vertical transfer clock, horizon-
tal transfer clock and electronic shutter clock) which driver
the CCD.
IC902 is an inverter IC which drives the horizontal CCDs (H1
and H2). In addition the XV1-XV3 signals which are output
from IC102 are the vertical transfer clocks, and the XSG1
and XSG signal which is output from IC102 is superimposed
onto XV2A and XV2B at IC907 in order to generate a ternary
pulse. In addition, the XSUB signal which is output from IC102
is used as the sweep pulse for the electronic shutter, and the
RG signal which is output from IC102 is the reset gate clock.
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to
Pins (26) and (27) of IC905. There are S/H blocks inside IC905
generated from the XSHP and XSHD pulses, and it is here
that CDS (correlated double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier. It is A/C converted internally into
a 10-bit signal, and is then input to IC102 of the CA2 circuit
board. The gain of the AGC amplifier is controlled by the volt-
age at pin (29) which is output from IC102 of the CA2 circuit
board and smoothed by the PWM.
Fig. 1-5. IC905 Block Diagram
1
18
10
9
8
7
6
5
4
3
2
14
15
16
17
20
19
11
12
13
SHT
V3B
V
L
V3A
V
H
V1B
V1A
GND
V4
V2
XV2
V
DD
XSHT
XSG3B
XSG3A
XV1
XSG1B
XSG1A
XV4
Input
Buffer
XV3
PBLK
SHP
DAC2
3-W INTF ADCIN AUXIN ACLP
PGACONT1-2
CLPOB
CCDIN
CLPDM
DAC1
DOUT
AUXCONT
VRT
SHD
PGA
VRB
CDS
CLP
8B DAC
8B DAC
10B DAC
INTF
MUX
PGA
TIMING
CLP
S/H
ADC
CLP
REF
10
3
0-10 dB
0-30 dB
ADCCLK
