Mach-DSP User’s Manual
Document Number: MACH-DSP-9021
Page 12
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XY2-100-compatible protocol
Refer to the diagram below, which illustrates the signals and phase relationships.
Looking at the diagram above, you will note that signals that are
sent to
the Mach-DSP
must change on the low-to-high transition of the clock; signals are
observed by
the
Mach-DSP on the high-to-low transitions of the clock.
Reception of a new Input Command begins when the Frame Sync line is brought high,
followed by a high-to-low transition of the Clock line. During this same high-to-low clock
transition, the first bit of data is also latched by the Mach-DSP. (Technically this is called
“active-high, late frame sync” because the sync signal coincides with data reception.)
Once the Frame Sync line has been detected high, it can remain high during the next 18
clocks, or it may be brought low again. In any event, the Frame Sync line must be
brought low by clock number 20, as shown in the diagram above, otherwise a Frame
Sync Error will occur, and data will not be communicated correctly. In essence, all of
this means that the data is “framed” in 20-clock sequences.
The Clock line can be any frequency up to a theoretical maximum of 25MHz, with any
reasonable duty cycle. The data frames described above may occur in sequence, one
after another (called “coherent frames”), or they may be sporadic (called “isolated
frames”). If they are sporadic, the Clock line may continue clocking in between data
frames, or it may be quiescent (preferably held in a low state). In all cases, whether the
clock is operational or not, the Frame Sync line must be held low when data is not sent.
The “frame rate” may be anything that the Clock and Frame Sync signals allow –
ranging from slower than one frame per hour up to a theoretical maximum of 1,250,000
frames per second. The data communicated via this serial port is absorbed by the
Mach-DSP at the rate that it is sent, and – unless Synchronous Sampling is selected (as
described several pages below), there is no attempt to synchronize the Mach-DSP’s
servo sample clock (typically 100kHz to 300kHz) to the serial port signals.
