Mach-DSP User’s Manual
Document Number: MACH-DSP-9021
Page 16
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Note that it takes roughly 5.75uS for the analog-to-digital conversion to be completed,
and for the data to be read and processed. If Frame Sync is brought low after 5.75uS
(as shown in the screen shot below), then the position data that is returned will
correspond with the immediately preceding rising edge of the Frame Sync signal.
In this screen shot, Frame Sync is brought high for around 6.1 microseconds, then
Frame Sync is brought low and serial communication commences. The command input
data and the returned position data are both communicated at the same time, and on
the same edges of the clock.
The screen shot above shows 100kHz sample rate, which is reasonable for most
applications. To provide for synchronized sampling as well as complete data
transmission during the present frame, the clock rate needs to be at least 8.3MHz for a
100kHz sample rate.
Future Expansion and Alternative Protocols
It should be obvious that there is a great deal of flexibility built into the Mach-DSP, and a
variety of custom applications and alternatives are possible. The number of bits used
and the polarity of Clock and Frame Sync signals are all easily changed. Please contact
us if you have special requirements, since they may be accommodated via firmware
updates, which are easily performed by users in the field.
