5-2
Trip and Target Logic
Date Code 20011205
SEL-311B Instruction Manual
From Figure 5.3
Figure 5.1: Trip Logic
Set Trip
Refer to Figure 5.1. All trip conditions:
·
Direct Transfer Trip
·
Switch-Onto-Fault Trip
·
Other Trips
are combined into OR-1 gate. The output of OR-1 gate asserts Relay Word bit TRIP to logical 1,
regardless of other trip logic conditions. It also is routed into the Minimum Trip Duration Timer
(setting TDURD).
As shown in the time line example in Figure 5.2, the Minimum Trip Duration Timer (with setting
TDURD) outputs a logical 1 for a time duration of “TDURD” cycles any time it sees a rising
edge on its input (logical 0 to logical 1 transition), if it is not already timing (timer is reset). The
TDURD timer ensures that the TRIP Relay Word bit remains asserted at logical 1 for a minimum
of “TDURD” cycles. If the output of OR-1 gate is logical 1 beyond the TDURD time, Relay
Word bit TRIP remains asserted at logical 1 for as long as the output of OR-1 gate remains at
logical 1, regardless of other trip logic conditions.
The Minimum Trip Duration Timer can be set no less than 4 cycles.
Summary of Contents for SEL-311B
Page 6: ......
Page 8: ......
Page 10: ......
Page 24: ......
Page 26: ......
Page 122: ......
Page 124: ......
Page 138: ......
Page 168: ......
Page 172: ......
Page 254: ......
Page 282: ......
Page 306: ......
Page 348: ......
Page 364: ......
Page 366: ......
Page 448: ......
Page 460: ......
Page 466: ......
Page 476: ......
Page 482: ......
Page 494: ......
Page 500: ......
Page 522: ......
Page 526: ......
Page 528: ......
Page 534: ......
Page 536: ......
Page 550: ......
Page 570: ......
Page 586: ......
Page 600: ......