4.176
SEL-700G Relay
Instruction Manual
Date Code 20170814
Protection and Logic Functions
Group Settings (SET Command)
Phase Matching
In some cases (that is, either 25SLO or 25SHI is set /- 0.02 Hz), the
correction pulses described previously in Frequency Matching are likely to
stop when the slip is very close to zero. This prevents the synchronism-check
function from asserting the bit 25C if the phase angle difference between
Vpxc and VS is not acceptable and is nearly static. The SEL-700G includes a
phase angle matching logic to automatically detect this condition and produce
kick pulses to raise or lower the slip, as shown in Figure 4.116. Set
KPLSMIND, KPLSMAXD, and KPULSEI to define minimum / maximum
kick pulse width and interval. Refer to the governor data sheet for relevant
information.
Voltage Matching
Refer to Figure 4.117 for a functional block diagram of the voltage matching
function.
The SEL-700G autosynchronism adjusts the generator voltage to match the
system voltage. The relay compares generator voltage magnitude to that of the
system/bus and asserts a Relay Word bit VRAISE or VLOWER, as necessary.
The VRAISE and VLOWER bits provide correction pulses to facilitate
voltage matching. You must assign these bits to the necessary outputs (for
example, OUT303 etc., see Table 4.61 for detail) connected to the exciter/
voltage regulator to control the generator voltage.
The relay computes the width of each correction pulse, as shown in
Figure 4.117. This width is proportional to how far the magnitude is from the
target magnitude. Set VADJRATE equal to the exciter/voltage regulator's rate
of response to the control pulses. Also, set VPLSMIND and VPLSMAXD to
define the minimum and maximum limits of the computed pulse widths.
Figure 4.117
Simplified Block Diagram, Voltage Matching Elements
NOTE:
The SEL-700G accurately
measures the “phase angle
difference” when the slip is within
+/- 1.00 Hz. If the slip is outside this
window, the measured angle
difference has no significance.
q
See Figure 4.105
Logic Activation
Activate
De-activate
(Higher Priority)
Relay
Word
Bits
VSYNCT
1
sec
Measured
Voltages
Vpxc
VS
VSYNCACT
VSYNCTO
VRAISE
VLOWER
Note: The logic is enabled when settngs E25X := YES and EAUTO := DIG.
The logic is de-activated and disabled when any of the following is true:
• Relay Word bit ASP, 52AX, TRIPX, BSYNCHX, or VSYNCTO is asserted.
• Relay Word bit 59VSX is deasserted.
• Both Relay Word bit FREQTRKX and ZCFREQX are deasserted.
Pulse
Generator
GENVLO = 1
GENVHI = 1
See Note
Pulse Definition Processing
(Pulse width = 0 except as computed below)
If Relay Word bit VDIFX = 0 (when 25VDIFX
≠
OFF)
or
If Relay Word bit 59VPX = 0 (when 25VDIFX := OFF):
Target magnitude of Vpxc = |VS|
Pulse Width
*
= |(|VS|
−
|Vpxc|)| / VADJRATE
Pulse Interval = VPULSEI
*
VPLSMIND
≤
Pulse Width
≤
VPLSMAXD
1
1
Pulse Width
Pulse Width
Pulse Interval
Pulse Interval
Relay
Word
Bit
AST
VSYNCST
Setting
Summary of Contents for SEL-700G Series
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