F.37
Date Code 20170814
Instruction Manual
SEL-700G Relay
IEC 61850 Communications
Logical Nodes
RMBAGGIO8
Ind01.stVal–Ind08.stVal
RMB1A–RMB8A
Receive M
IRRORED
B
ITS
(RMB1A to RMB8A)
RMBBGGIO10
Ind01.stVal–Ind08.stVal
RMB1B–RMB8B
Receive M
IRRORED
B
ITS
(RMB1B to RMB8B)
SVGGIO3
Ind01.stVal–Ind32.stVal
SV01–SV32
e
SEL
OGIC
Variables (SV01 to SV32)
SVTGGIO4
Ind01.stVal–Ind32.stVal
SV01T–SV32T
g
SEL
OGIC
Variable Timers (SV01T to SV32T)
SYNGGIO24
Ind01.stVal
AST
Autosynchronism start
SYNGGIO24
Ind02.stVal
ASP
Autosynchronism stop
SYNGGIO24
Ind03.stVal
FSYNCTO
Frequency synch timer timeout
SYNGGIO24
Ind04.stVal
FSYNCACT
Frequency matching–auto synchronization is in
progress
SYNGGIO24
Ind05.stVal
FRAISE
Raise frequency for autosynchronism
SYNGGIO24
Ind06.stVal
FLOWER
Lower frequency for autosynchronism
SYNGGIO24
Ind07.stVal
VSYNCTO
Voltage synch timer timeout
SYNGGIO24
Ind08.stVal
VSYNCACT
Voltage matching–auto synchronization is in progress
SYNGGIO24
Ind09.stVal
VRAISE
Raise voltage for autosynchronism
SYNGGIO24
Ind10.stVal
VLOWER
Lower voltage for autosynchronism
SYNGGIO24
Ind11.stVal
59VPX
Generator terminal voltage within voltage window
SYNGGIO24
Ind12.stVal
59VSX
System voltage within voltage window
SYNGGIO24
Ind13.stVal
VDIFX
Generator and system voltage difference within
acceptable bounds
SYNGGIO24
Ind14.stVal
SFX
Generator slip frequency is within acceptable bounds
(between 25SLO and 25SHI settings)
SYNGGIO24
Ind15.stVal
25AX1
Generator slip/breaker-time compensated phase angle
less than 25ANG1X setting
SYNGGIO24
Ind16.stVal
25AX2
Generator uncompensated phase angle less than
25ANG2X setting
SYNGGIO24
Ind17.stVal
GENVHI
Generator voltage greater than system voltage
SYNGGIO24
Ind18.stVal
GENVLO
Generator voltage less than system voltage
SYNGGIO24
Ind19.stVal
GENFHI
Slip frequency greater than 25SHI setting
SYNGGIO24
Ind20.stVal
GENFLO
Slip frequency less than 25SLO setting
SYNGGIO24
Ind21.stVal
59VPY
Intertie terminal voltage within voltage window
SYNGGIO24
Ind22.stVal
59VSY
System voltage within voltage window
SYNGGIO24
Ind23.stVal
VDIFY
Intertie and system voltage difference within
acceptable bounds
SYNGGIO24
Ind24.stVal
SFY
Intertie slip frequency within acceptable bounds
(less than 25SF setting)
SYNGGIO24
Ind25.stVal
25AY1
Intertie slip/breaker-time compensated phase angle
less than 25ANG1Y setting
SYNGGIO24
Ind26.stVal
25AY2
Intertie slip/breaker-time compensated phase angle
less than 25ANG1Y setting
SYNGGIO24
Ind27.stVal–Ind32.stVal
0
Reserved for future use
TLEDGGIO6
Ind01.stVal
ENABLED
ENABLED LED
TLEDGGIO6
Ind02.stVal
TRIP_LED
TRIP LED
Table F.19
Logical Device: ANN (Annunciation)
(Sheet 4 of 5)
Logical Node
Attribute
Data Source
Comment
Summary of Contents for SEL-700G Series
Page 14: ...This page intentionally left blank ...
Page 22: ...This page intentionally left blank ...
Page 32: ...This page intentionally left blank ...
Page 52: ...This page intentionally left blank ...
Page 106: ...This page intentionally left blank ...
Page 510: ...This page intentionally left blank ...
Page 560: ...This page intentionally left blank ...
Page 578: ...This page intentionally left blank ...
Page 588: ...This page intentionally left blank ...
Page 604: ...This page intentionally left blank ...
Page 634: ...This page intentionally left blank ...
Page 738: ...This page intentionally left blank ...
Page 802: ...This page intentionally left blank ...