4.73
Date Code 20081022
Instruction Manual
SEL-787 Relay
Protection and Logic Functions
Logic Settings (SET L Command)
Figure 4.47
Logic Diagram of a Latch Switch
If setting SET
n
asserts to logical 1, latch bit LT
n
asserts to logical 1. If setting
RST
n
asserts to logical 1, latch bit LT
n
deasserts to logical 0. If both settings
SET
n
and RST
n
assert to logical 1, setting RST
n
has priority and latch bit LT
n
deasserts to logical 0. You can use these latch bits in SEL
OGIC
control
equations to create custom logic for your application.
The SEL-787 includes 32 latches.
shows the
SET
and
RESET
default settings for Latch 1 through Latch 4. The remaining latches are all set
to NA.
Latch Bits:
Nonvolatile State
Power Loss
The states of the latch bits (LT01–LT32) are retained if power to the device is
lost and then restored. If a latch bit is asserted (e.g., LT02 := logical 1) when
power is lost, it is asserted (LT02 := logical 1) when power is restored. If a
latch bit is deasserted (e.g., LT03 := logical 0) when power is lost, it is
deasserted (LT03 := logical 0) when power is restored.
Table 4.26
Latch Bits Equation Settings
Settings Prompt
Setting Range
Setting Name := Factory Default
SET01
SEL
OGIC
SET01 := R_TRIG SV01T AND NOT LT01
RST01
SEL
OGIC
RST01 := R_TRIG SV01T AND LT01
SET02
SEL
OGIC
SET02 := R_TRIG SV02T AND NOT LT02
AND PB02
RST02
SEL
OGIC
RST02 := R_TRIG SV02T AND LT02 AND
PB02
SET03
SEL
OGIC
SET03 := (PB03 AND R_TRIG SV02T)
AND LT01 AND NOT (52A1 AND NOT
LT02 OR 52A2 AND LT02)
RST03
SEL
OGIC
RST03 := (R_TRIG SV02T OR SV03T)
AND LT03
SET04
SEL
OGIC
SET04 := (PB04 AND R_TRIG SV02T)
AND (52A1 AND NOT LT02 OR 52A2
AND LT02)
RST04
SEL
OGIC
RST04 := (R_TRIG SV02T OR SV04T)
AND LT04
•
•
•
•
•
•
•
•
•
SET32
SEL
OGIC
SET32 := NA
RST32
SEL
OGIC
RST32 := NA
LTn
SETn
RSTn
(Set)
(Reset)
(n = 01 through 32)
Relay
Word
Bits
SEL
OGIC
Setting
Summary of Contents for SEL-787
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