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© Sealevel Systems, Inc. 5011 Manual | SL9167 12/2022
•
Off loads communication processing
•
OEM Security Feature available
IUSC™
The
ROUTE 56
adapter is based on a single Zilog Z16C32 IUSC (
I
ntegrated
U
niversal
S
erial
C
ontroller).
Application and driver software access the IUSC registers through the first 256 bytes of on-board RAM.
Register access to the IUSC can be disabled via I/O registers allowing the first 256 bytes of RAM to be used
for buffer storage. The IUSC has a built-in DMA controller that allows high-speed data transfers directly to
and from the 256K block of on-board memory. The IUSCs built-in DMA controller supports 4 different
modes of DMA transfer: Single Buffer, Pipelined, Array, and Link List. An on-board 16MHz oscillator clocks
the IUSC.
RAM
The
ROUTE 56
has 256K of on-board SRAM. The 256K bytes of SRAM appear to the host processor in the
2nd 512K bytes of the host’s memory address range, (Segment 80000 to F0000). This 256K of SRAM is in
a 16K bankswitched window. The address of the 16K window and the page is software selectable. The
IUSC always views the 256K of SRAM as linear memory. The SRAM can be selectively disabled through
software. The SRAM should be addressed in a section that does not conflict with system memory (i.e. I/O
adapters, Video Memory, BIOS/BIOS extensions.)
Low Address Mode
Selected
512K (80000)
1
MB (FFFFF
)
16
K Address Window
for Bank Switching
(D0000-D4000)
Summary of Contents for Route 56
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