CQ7-A30
CQ7-A30 - Rev. First Edition: 1.0 - Last Edition: 2.0 - Author: S.B. - Reviewed by G.G. Copyright © 2016 SECO S.r.l.
58
A30 carrier board, this signal is not directly connected to the Qseven
®
card edge connector
’
s signal LPC_CLK, but it comes out from a dedicated clock buffer. For
this reason, on connector CN3 it is not possible to use this signal line as General Purpose I/O #4.
LPC_FRAME#, LPC Frame indicator, active low output line. This signal is used to signal the start of a new cycle of transmission, or the termination of existing
cycles due to abort or time-out condition. Pin multiplexed with General Purpose I/O #5.
SERIRQ: LPC Serialised IRQ request, bidirectional line. This signal is used only by peripherals requiring Interrupt support. It is shared with general Purpose I/O #6.
LPC_LDRQ#: LPC DMA request, active low input line. This signal is used only by peripherals requiring DMA or bus mastering. It is shared with General Purpose I/O
#7
LPC_RST# signal is derived by PLT_RST# signal, by buffering it using a CMOS buffer.
3.3.19
POST Codes section
On x86 architectures, during the boot phase, usually the BIOS outputs on LPC bus some diagnostic progressive codes (a hexadecimal byte), which reflect the
status of the last performed operation. This sequence (Power On Self Test, POST) is therefore useful for debugging purposes in case the Qseven
®
module fails to
initialize properly. Indeed, in that case, the BIOS execution stops, and the last POST code transmitted is indicative of the point where the initialization failed.
For this reason on the CQ7-A30 board there are four seven-segment LCD display, which show the POST codes transmitted on ports 80h and
84h.
The POST codes are usually transmitted on LPC bus at addresses 80h and 84, but could be
available at addresses 90h and 94h. The selection of the address to be read is made using
jumper JP12, which is a standard pin header, P2.54mm, 1x3 pin, according to the table on the left.
JP12 position
POST Codes addresses
1-2
80h / 84h
2-3
90h / 94h
