SBC-C43
SBC-C43 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Author: A.R. - Reviewed by S.R. -Copyright © 2020 SECO S.p.A.
35
S/SATA0_RX-: Serial ATA Channel #0 Receive differential pair
10nF AC series decoupling capacitors are placed on each line of SATA differential pairs.
Here following the signals related to the PCI-e interface:
PC/PCIe0_Tx0-: PCI Express port #0 lane #0, Transmitting Output Differential pair
PC/PCIe0_Rx0-: PCI Express port #0 lane #0, Receiving Input Differential pair
PC/PCIe0_Tx1-: PCI Express port #0 lane #1, Transmitting Output Differential pair
PC/PCIe0_Rx1-: PCI Express port #0 lane #1, Receiving Input Differential pair
PCIe_K/ PCIe_KEYB_CLK-: PCI Express Reference Clock for port #0, Differential
Pair
PCIE_RST0#: Reset Signal that is sent from the SoC to all PCI-e devices available on the board.
It is a +3.3V_RUN active-
-down.
CLK_REQ0#: PCI Express Clock Request Input, active low signal. This signal shall be driven
low by any module inserted in the connectivity slot, in order to ensure that the SoC makes
available the reference clock. Electrical level +3.3V_RUN with a 47K pull-up resistor.
PCIe_WAKE0#:
-up resistor. It
must be externally driven by the Connectivity module plugged in the slot when it requires waking
up the system.
Here following the signals related to the USB interface:
/USB_P1-: USB Port #1 differential pair; it is managed by Microchip USB4604 Hub
1.
M2_KEYB_PWROFF#: Power Off signal for plugged modules, usually used in battery-powered
-up @ 1.8V_RUN.
M2_KEYB_W_DIS1#: M.2 module disable signal #1, active low output.
M2_KEYB_W_DIS1#: M.2 module disable signal #2, active low output.
UIM_RESET: Reset signal line, sent from M.2 WWAN card to the UIM module.
UIM_DATA: Bidirectional Data line between M.2 WWAN card and UIM module.
UIM_CLK: Clock line, output from M.2 WWAN card to the UIM module.
UIM_PWR: Power line for UIM module.
SIM_DETECT: Sim Detect output, sent to the WWAN module to signal insertion or removal of the SIM in the slot. This pin can also be forced to be low through the
jumper JP1
31
PC
32
UIM_CLK
33
GND
34
UIM_DATA
35
PCIe0_Tx1-
36
UIM_PWR
37
PC
38
---
39
GND
40
---
41
PCIe0_Rx0-/S
42
---
43
PC/SATA0_RX-
44
---
45
GND
46
---
47
PCIe0_Tx0-/SATA0_TX-
48
---
49
PC/S
50
PCIE_RST0#
51
GND
52
CLK_REQ0#
53
PCIe_K
54
PCIe_WAKE0#
55
PCIe_ KEYB_CLK-
56
---
57
GND
58
---
59
---
60
---
61
---
62
---
63
---
64
---
65
---
66
SIM_DETECT
67
---
68
---
69
CONF1
70
+3.3V_RUN
71
GND
72
+3.3V_RUN
73
GND
74
+3.3V_RUN
75
CONF2
