THEMIS
THEMIS User Manual - Rev. First Edition: 1.0 - Last Edition: 2.2 - Author: A.R. - Reviewed by S.R. -Copyright © 2022 SECO S.p.A.
34
M.2 SSD/WWAN Slot: Socket 2 Key B
The mass storage capabilities of the THEMIS board are completed by an M.2 SSD Slot, which allow plugging M.2 Socket 2 Key B
Solid State Drives.
The same slot can be used alternatively for the connection of
Connectivity modules, using PCI-e x2 interface or USB 2.0
interface (USB interface is always available, while SATA
interface is alternative to PCI-e interface).
The connector used for the M.2 SSD slot is CN37, which is a
standard 75 pin M.2 Key B connector, type LOTES p/n
APCI0087-P001A, H=8.5mm, with the pinout shown in the
table on the left.
On the THEMIS board there is also a Threaded Spacer which allows the placement of M.2
Socket 2 Key B SSD modules in 2260 size.
It is possible to place also modules in 2242 / 3042 size, by using a M/F Spacer which allow
fixing the M.2 SSD on the spacer already available on the PCB, deemed for the fixing of the
M.2 connectivity slot (see par. 3.3.8).
Here following the signals related to the SATA interface:
S / SATA0_TX-: Serial ATA Channel #0 Transmit differential pair
S / SATA0_RX-: Serial ATA Channel #0 Receive differential pair
10nF AC series decoupling capacitors are placed on each line of SATA differential pairs.
Here following the signals related to the PCI-e interface:
PC / PCIE0_TX0-: PCI Express port #0 lane #0, Transmitting Output Differential pair
PC / PCIE0_RX0-: PCI Express port #0 lane #0, Receiving Input Differential pair
PC / PCIE0_TX1-: PCI Express port #0 lane #1, Transmitting Output Differential pair
PC / PCIE0_RX1-: PCI Express port #0 lane #1, Receiving Input Differential pair
PCIE_K / PCIE_KEYB_CLK-: Dedicated PCI Express Reference Clock
PCIE_CTL0_RST: Reset Signal that is sent from the SoC to all PCI-e devices available on the
board. It is a +3.3V_RUN active-low signal with 100k
Ω
pull-down.
PCIE_CTL0_CLK_REQ0: PCI Express Clock Request Input, active low signal. This signal shall
be driven low by any module inserted in the connectivity slot, in order to ensure that the SoC
makes available the reference clock. Electrical level +3.3V_RUN with a 47K
Ω
pull-up resistor.
M.2 SSD/WWAN Slot (Socket 2 Key B type 3042/2260- CN37)
Pin Signal
Pin Signal
1
CONFIG3
2
+3.3V_RUN
3
GND
4
+3.3V_RUN
5
GND
6
M2_KEYB_PWROFF#
7
USB_P1-
8
M2_KEYB_W_DIS1#
9
10
---
11
GND
20
---
21
CONF0
22
---
23
---
24
---
25
---
26
M2_KEYB_W_DIS2#
27
GND
28
---
29
PCIE0_RX1-
30
UIM_RESET
31
PC
32
UIM_CLK
33
GND
34
UIM_DATA
35
PCIE0_TX1-
36
UIM_PWR
37
PC
38
---
39
GND
40
---
41
PCIE0_RX0- / S 42
---
43
PC / SATA0_RX- 44
---
45
GND
46
---
47
PCIE0_TX0- / SATA0_TX-
48
---
