Sel 751A Instruction Manual Download

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4.72

SEL-751A Relay

Instruction Manual

Date Code 20100129

Protection and Logic Functions

Reclose Logic

EXAMPLE 4.15

Factory Settings Example

The reset timing is blocked if Relay Word bit TRIP is asserted,
regardless of the reclosing relay state:

79BRS :=

TRIP

EXAMPLE 4.16

Additional Settings Example 1

The block reset timing setting is:

79BRS :=

(51P1P OR 51G1P) AND 79CY

Relay Word bit 79CY corresponds to the Reclose Cycle State. The
reclosing relay is in one of the three reclosing relay states at any one
time (see

Figure 4.34

and

Table 4.26

When the relay is in the Reset or Lockout States, Relay Word bit 79CY
is deasserted to logical 0. Thus, the 79BRS setting has no effect when
the relay is in the Reset or Lockout States. When a circuit breaker is
closed from lockout, there could be cold load inrush current that
momentarily picks up a time-overcurrent element [e.g., phase time-
overcurrent element 51P1 pickup (51P1P) asserts momentarily]. But,
this assertion has no effect on reset timing because the relay is in the
Lockout State (79CY = logical 0). The relay will time immediately on
reset time 79RSLD and take the relay from the Lockout State to the
Reset State with no additional delay because 79BRS is deasserted to
logical 0.

When the relay is in the Reclose Cycle State, Relay Word bit 79CY is
asserted to logical 1. Thus, the example 79BRS setting can function to
block reset timing if time-overcurrent pickup 51P1P or 51G1P is picked
up while the relay is in the Reclose Cycle State. This helps prevent
repetitive “trip-reclose” cycling.

EXAMPLE 4.17

Additional Settings Example 2

If the block reset timing setting is:

79BRS :=

51P1P OR 51G1P

then reset timing is blocked if time-overcurrent pickup 51P1P or 51G1P
is picked up, regardless of the reclosing relay state.

Sequence
Coordination Setting
(79SEQ)

The sequence coordination setting 79SEQ keeps the relay in step with a
downstream line recloser in a sequence coordination scheme, which prevents
overreaching SEL-751A overcurrent elements from tripping for faults beyond
the line recloser. This is accomplished by incrementing the shot counter and
supervising overcurrent elements with resultant shot counter elements.

In order for the sequence coordination setting 79SEQ to increment the shot
counter,

both

the following conditions must be true:

➤

No trip present (Relay Word bit TRIP = logical 0)

➤

Circuit breaker closed (SEL

OGIC

control equation setting 52A

= logical 1, effectively)

The sequence coordination setting 79SEQ is usually set with some overcurrent
element pickups. If the above two conditions are both true, and a set
overcurrent element pickup asserts for at least 1.25 cycles and then deasserts,
the shot counter increments by one count. This assertion/deassertion indicates
that a downstream device (e.g., line recloser—see

Figure 4.37

) has operated to

clear a fault. Incrementing the shot counter keeps the SEL-751A “in step”
with the downstream device, as is shown in

Additional Settings Example 1 on

page 4.73

and

Additional Settings Example 2 on page 4.74

Every time a sequence coordination operation occurs, the shot counter is
incremented, and the reset timer is loaded up with reset time 79RSD.
Sequence coordination can increment the shot counter beyond last shot, but no

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