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AK - 44
CHASSIS
composed of an integrated VCO (12 MHz) that requires the chroma Reference frequency (4.43 MHz or 3.58 MHz
crystal oscillator reference signal), a divider by 768, a line decoder, and a phase comparator.
• PLL2: The second phase locked loop that controls the phase of the horizontal output (Compensation of horizontal
deflection transistor storage time variation). Also the horizontal position adjustment is also performed in PLL2.
• A vertical pulse extractor.
• A vertical countdown system to generate all vertical windows (vertical synchronization window, frame blanking pulses,
50/60 Hz identification window...).
• Automatic identification of 50/60 Hz scanning.
• PLL1 time constant control.
• Noise detector, video identification circuits, and horizontal coincidence detector.
• Vertical output stage including de-interlace function, vertical position control.
• Vertical amplitude control voltage output (combined with chroma reference output and Xtal 1 indication).
2.7 Chroma and luminance processing
The chroma decoder is able to demodulate PAL, NTSC and SECAM signals.
The decoder dedicated to PAL and NTSC sub-carrier is based on a synchronous demodulator, and an Xtal PLL locked
on the phase reference signal (burst).
The SECAM demodulation is based on a PLL with automatic calibration loop.
The color standard identification is based on the burst recognition.
Automatic and forced modes can be selected through the I2C bus.
NTSC tint, and auto flesh are controlled through I2C bus.
Xtal PLL can handle up to 3 crystals to work in PAL M, PAL N and NTSC M for South America.
ACC an ACC overload control the chroma sub-carrier amplitude within 26dB range. Both ACCs are based on digital
systems and do not need external capacitor.
All chroma filters are fully integrated and tuned via a PLL locked on Xtal VCO signal.
A second PLL is used for accurate fine-tuning of the SECAM bell filter. This tuning is achieved during the frame blanking.
An external capacitor memorizes the bell filter tuning voltage.
A base-band chroma delay-line rebuilds the missing color line in SECAM and removes transmission phase errors in
PAL.
The base-band chroma delay line is clocked with 6 MHz signal provided by the horizontal scanning VCO.
The luminance processor is composed of a chroma trap filter, a luminance delay line, a peaking function with noise
coring feature, a black stretch circuit.
Trap filter and luminance delay lines are achieved with the use of bi-quad integrated filters, autoaligned via a master
filter phase locked loop.
2.8 RGB output circuit
The video processor performs the R, G, B processing.
There are three sources:
1. Y, U, V inputs (coming from luma part (Y output), and chroma decoder outputs (R-Y, B-Y outputs).
2. External R, G, B inputs from SCART (converted internally in Y, U, V), with also the possibility to input YUV
signals from a DVD player, (YUV specification is Y= 0.7 V PP , U= 0.7 V PP , V = 0.7 V PP for 100% color
bar).
3. Internal R, G, B inputs (for OSD and Teletext display)
The main functions of the video part are:
- Y, U, V inputs with integrated clamp loop, allowing a DC link with YUV outputs,
- External RGB inputs (RGB to YUV conversion), or direct YUV inputs,
- Y, U, V switches,
- Contrast, saturation, brightness controls,
- YUV to RGB matrix,
- OSD RGB input stages (with contrast control),
- RGB switches,
- APR function,
- DC adjustment of red and green channels,
- Drive adjustments (R, G, B gain),
- Digital automatic cut-off loop control,
- Manual cut-off capability with I2C adjustments,
- Half tone, oversize blanking, external insertion detection, blue screen,
- Blanking control and RGB output stages.
Summary of Contents for 21LF-90N
Page 6: ...6 21LF 90N CHASSIS LAYOUT Mother Unit CRT Unit Headphone Unit ...
Page 48: ...36 AK 44 CHASSIS 1 I H G F E D C B A 2 3 4 5 6 7 18 4 Schematic Diagram of Audio Circuit ...
Page 52: ...40 AK 44 CHASSIS 1 I H G F E D C B A 2 3 4 5 6 7 18 7 Schematic Diagram of CRT Socket Circuit ...
Page 55: ...43 AK 44 CHASSIS Notes ...
