CD-C622/C2900
– 50 –
IC2 VHiLC78622N-1: Servo/Signal Control (LC78622NE) (2/2)
47*
SBSY
Output
Sub-code clock sync signal output terminal.
48*
EFLG
Output
C1, C2, single, double correction monitor terminal.
49*
PW
Output
Sub-code P, Q, R, S, T, U, and W output terminal.
50*
SFSY
Output
Sub-code frame sync signal output terminal. Falling occurs when the sub-code is in standby state.
51
SBCK
Input
Sub-code read clock input terminal. Schmidt input (When this terminal is not used, connect it to 0V.)
52*
FSX
Output
7.35 kHz sync signal (frequency-divided from crystal oscillation) output terminal.
53
WRQ
Output
Sub-code Q output standby output terminal.
54
RWC
Input
Read/Write control input terminal. Schmidt input.
55
SQOUT
Output
Sub-code Q output terminal.
56
COIN
Input
Command input terminal from microcomputer.
57
CQCK
Input
Command input taking-in clock or sub-code taking-out (from SQOUT) clock input terminal.
Schmidt input
58
RES
Input
LSI resetting input terminal. When power is turned on, once "L" is set.
59*
TEST11
Output
Output terminal for test. Use this terminal in open state (usually "L" output).
60*
16M
Output
16.9344 MHz output terminal.
61
4.2M
Output
4.2336 MHz output terminal.
62
TEST5
Input
Input terminal for test. Pull-down resistor built-in. Be sure to connect this terminal to 0V.
63
CS
Input
Chip selection input terminal. Pull-down resistor built-in.
In noncontrol state connect this terminal to 0V.
64
TEST1
Input
Input terminal for test. Pull-down resistor is not provided. Be sure to connect this terminal to 0V.
Note: The same potential must be supplied to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Figure 50 BLOCK DIAGRAM OF IC
Pin
No.
Function
Terminal Name Input/Output
DEFI
EFMIN
FSEQ
V/P
PW
SBCK
SBSY
SFSY
CS
WRQ
SQOUT
COIN
RWC
CQCK
HFL
TES
TOFF
JP-
JP+
RES
TGL
CONT1
PCCL
CONT2
CONT3
CONT4
CONT5
EMPH/CONT6
EFLG
16M
4.2M
XVss
FSX
XIN
XOUT
XV
DD
RVss
RV
DD
MUTER/CONT7
RCHO
LCHO
MUTEL/CONT8
LVss
LV
DD
DOUT
C2F
EFMO
VV
DD
VVss
PDO
I SET
FR
PCK
TAI
TST11
TEST1
TEST2
TEST3
TEST4
TEST5
V
DD
Vss
CLV+
CLV-
Slice level
control
VCO colck oscillation
clock control
2 K x 8 b i t
R A M
RAM address
generator
Interpolation mute
Bilingual
Digital OUT
Digital
attenuator
X4 oversampling
digital filter
1 b i t D A C
L . P . F
XTAL system timing
generator
General-use port
Servo commander
µ
C O M
Interface
Subcode division
QCRC
C L V
Digital servo
Sync detection
EFM demodulation
Flag processing of C1/C2
error detection and correction
Summary of Contents for CD-C2900
Page 71: ...CD C622 C2900 71 16 M E M O ...
