64
DV-NC55U/C/M
Refresh
Interval Timer
Refresh
Counter
Self Refresh Counter
Address
Register
Burst Length
Counter
Column Addr.
Latch & Counter
512Kx16
Bank 1
Column Decoder
Sense AMP & I/O gates
Column Decoder
Sense AMP & I/O gates
Mode Register
Test Mode
I/O Control
512Kx16
Bank 0
Row Addr. Latch/Predecode
Row Addr. Latch/Predecode
State Machine
Data Input/Output Buffers
Row Decoder
Precharge
Row Active
Column Active
Overflow
Address[0:10]
Audio/Self Refresh
Ref. Addr.[0:11]
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK
CKE
BS(A11)
CS
RAS
CAS
WE
DOMU
DOML
35
CLK
Clock
The system clock input. All other inputs are referenced to the SDRAM on
the rising edge of CLK.
34
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will
be one of the states among power down, suspend or self refresh.
18
CS
Chip Select
Command input enable or mask except CLK, CKE and DOM
19
BS
Bank Address
Select either one of banks during both RAS and CAS activity.
20~24
A0~A10
Address
Row Address: RA0~RA10, Column Address: CA0~CA7
27~32
17, 16, 15
RAS, CAS, WE
Row Address Strobe,
RAS, CAS and WE define the operation.
Column Address Strobe,
Refer function truth table for details.
Write Enable
14, 36
DOML, DOMU
Data Input/Output Mask
DOM control output buffer in read mode and mask input data in write mode.
2, 3, 5,
I/O0~15
Data Input/Output
Multiplexed data input/output pin
6, 8, 9, 11, 12, 39, 40,
42, 43, 45, 46, 48, 49
VCC/VSS
Power Supply/Ground
Power supply for internal circuit and input buffer.
1, 25, 26
4, 7, 10,
VCCO/VSSO
Data Output Power/Ground Power supply for DO
13, 38, 41, 44, 47, 50
33, 37
NC
No Connection
No connection
11-7. IC602-3 IX3455CE 16M SDRAM
Pin No.
Terminal Name
Name
Input Function
• Block Diagram
