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LC-24LE250
LC-22LE250
-Multi-page program time (2 pages):
200us / 250us (3.0V/1.8V, Typ.)
BLOCK ERASE / MULTIPLE BLOCK ERASE
-Block erase time:
3.5 ms (Typ)
-Multi-block erase time (2 blocks):
3.5ms/ 3.5ms (3.0V/1.8V, Typ.)
SEQURITY
-OTP area
-Serial number (unique ID)
-Hardware program/erase disabled during Power transition
-Multiplane Architecture:
Array is split into two independent planes.
Parallel operations on both planes are available, having program and erase time.
-Single and multiplane copy back program with automatic
EDC (error detection code)
-Single and multiplane page re-program
-Single and multiplane cache program
-Cache read
-Multiplane block erase
Reliability
-100,000 Program / Erase cycles (with 1bit /528Byte ECC)
-10 Year Data retention
ONFI 1.0 COMPLIANT COMMAND SET
ELECTRONICAL SIGNATURE
-Maunufacture ID: ADh
-Device ID
PACKAGE
-Lead/Halogen Free
-TSOP48 12 x 20 x 1.2 mm
-FBGA63 9 x 11 x 1.0 mm
b) Description
H27(U_S)2G8_6F2C series is a 256Mx8bit with spare 8Mx8 bit capacity. The device is offered in
3.0/1.8 Vcc Power Supply, and with x8 and x16 I/O interface Its NAND cell provides the most
cost-effective solution for the solid state mass storage market. The memory is divided into blocks that
can be erased independently so it is possible to preserve valid data while old data is erased.
The device contains 2048 blocks, composed by 64 pages. Memory array is split into 2 planes, each
of them consisting of 1024 blocks. Like all other 2KB -page NAND Flash devices, a program operation
allows to write the 2112-byte page in typical 200us(3.3V) and an erase operation can be performed in
typical 3.5ms on a 128K-byte block. In addition to this, thanks to multi-plane architecture, it is possible
to program 2 pages at a time (one per each plane) or to erase 2 blocks at a time (again, one per each
plane). As a consequence, multi-plane architecture allows program time to be reduced by 40% and
erase time to be reduction by 50%. In case of multi-plane operation, there is small degradation at 1.8V
application in terms of program/erase time.
The multiplane operations are supported both with traditional and ONFI 1.0 protocols. Data in the
page can be read out at 25ns (3V version) and 45ns (1.8V version) cycle time per byte. The I/O pins
serve as the ports for address and data input/output as well as command input. This interface allows a
reduced pin count and easy migration towards different densities, without any rearrangement of
footprint. Commands, Data and Addresses are synchronously introduced using CE#, WE#, ALE and
Summary of Contents for LC-24LE250V-BK
Page 12: ...12 LC 24LE250 LC 22LE250 DIMENSIONS English 20 Dimensional Drawings LC 22LE250 ...
Page 13: ...13 LC 22LE250 LC 24LE250 English 21 Dimensional Drawings LC 24LE250 ...
Page 16: ...16 LC 24LE250 LC 22LE250 3 Remove Speaker Wire 4 Remove AC Cord ...
Page 18: ...18 LC 24LE250 LC 22LE250 1 1 General Block Diagram 15 General Block Diagram ...
Page 19: ...19 LC 22LE250 LC 24LE250 1 2 Placement of Blocks ...
Page 22: ...22 LC 24LE250 LC 22LE250 ...
Page 25: ...25 LC 22LE250 LC 24LE250 10 Table 2 Pin functions ...
Page 32: ...32 LC 24LE250 LC 22LE250 17 Table 5 Recommended operating conditions Figure 7 Pin description ...
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Page 63: ...63 LC 22LE250 LC 24LE250 MENU Return Exit Ret Back SRS Video Settings ...
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