Sharp MZ-3500, Service Manual

Page 1: ...e Memory Configuration 7 3 CPU and memory 12 4 CRT display 25 5 MFD interface 52 6 R232C interface 72 7 Printer interface 78 8 Other interface 81 9 Power circuit discnption 87 10 Keyboard controller circuit discriptlOn 90 11 Self check functions 94 12 IPL flow chart 103 13 Circuit diagram P W S Parts list Guide SHARP CORPORATION ...

Page 2: ...H SP6102ROOl Custom LSI Screen controller CSP l SP6102COO2 CSP 2 SP6102COO3 GDC CRT controller jJPD7220 I O FDC Floppy disk controller jJPD765 PlO Parallel I O port 8255 SIO Serial I O port 8251 TIMER Counter 8253 CLOCK Clock jJPDI990AC Screen structure 80 characters x 25 hnes 80 x 20 40 x 25 or 40 x 20 Elements 8 x 16 8 x 8 DISPLAY Attribute Reverse blink hne hOrizontal vertIcal Colors 8 colors o...

Page 3: ...s after 12 1Two key rollover Other continuous depression of the same key_ Indicators 4 LED s POWER Alphanumeric keys Molded I Color Office gray Cabinet Size W x H x LI 467 x 35 x 190 1 Weight 1 About 1_5kg 3_3 Ib Keyboard layout Refer to the page 7IN CIRCUIT DIAGRAM 1 3 MZ 1U02 Expansion unit for the MZ 3500 series CPU which can be attached to the rear side of the main unit_ Outline Optional board...

Page 4: ...tor Two screens video unit is in use 640 x 400 640 x 400 dots 640 x 400 dots green monitor One screen Three screens 640 x 400 640 x 400 dots color monitor One screen SDISP Screen designation for two video units BASIC graphic control statements ODISP Designation of output screen Software CHANGE DISP Mode designation GCOLOR Graphic pattern designation CLS Cleared by the color specified PSET Dot set ...

Page 5: ...up to a ma imum of 256 KB This option plug into the e pantion bo in slot 1 or 3 Basic I 64KDRAM x 8 64KBI LSI I 64KDRAM x 8 128KB Specifications E pansion Memory and user Main CPU only Use of MZ 1R06 Using eight 64K RAM s area on the MZ 1R06 Total capacity of 128 KB 192 KB 256 KB the main CPU RAM SYSTEM 57 KB BASIC AREA RAM USER BASE AREA 80 KB 128 KB 208 KB Y 4 ...

Page 6: ...ng PERSISTANCE Total number 01 I2 000 characters 1 Display capacity dISplay characters 80 characters x 25 Imes 220 x 145 Method Separate mput TTL level HOrizontal 2086kHz Vertical JW power consumption Molded Color IOffice gray Size W x H x Ll 324x310x356 Weight 3 Vertical synchronization contrast brightness CPU connection cable and power cord and Tilt stand N N N MZ3500 I 12 90 0 deflection 1 640 ...

Page 7: ...rinter MZ 1P04 r I p r I ronter I I CE 332P I r l Cable 1_____ J r MZ 1C03 r 1 Printer I 1 102824E I I _____ J Model 3531 Cable Option MFO MZ 1C07 MZ 1F02 Option MFO MZ 1F03 Cable I OptIon MFOI MZ 1COO CE 331M I I L ____ J RS 232C RS232C I F r Cable MZ 1EOl MZ 1C05 I GP I O Cable MZ 1E02 MZ 1C19 Expansion f unit MZ 1U02 r SFO IF OptIon SFO Option SFO MZ 1E03 MZ 1F05 MZ 1F05 Option RAM PWB Option R...

Page 8: ... COOO BFFF 8000 7FFF RAMA 4 RAMA 3 RAMA 2 4000 3FFF I I ROMB I I 2000 L ____J RAMA 1 OFFF EJ ROM IPL _ 0000 2 1 SOO INITIALIZE STATE SOO can only exist immediately after power on and the system executes IPL under this condition and that the system thus loaded will automatically assign memory area for SOl S02 and S03 SUB CPU MSl O L MSO O L L ____ I I I ROM I SPAPE I I I RAM so RAM SC RAM SB RAM SA...

Page 9: ... RAM COM is shared by both the main CPU and the sub CPU INITIALIZE FLOW START Lwd 800TSTRAP A ll TART ll 4 JAf I T wf r control to the BOOTSTRAP Tf1II Ifef SUB CPU sv rr Pf ograt n to lh sus CPU 11 I 8 2 The main CPU then terminates resetting the sub CPU and starts the sub CPU At the same time the ROM IPL is assigned to the sub CPU 3 The main CPU then send the memory allocation state to SD1 and st...

Page 10: ...ress 0000 of the sub CPU is ROM address 0000 The memory area above ROM address 1000 cannot be used by the sub CPU because the main CPU initial program has been loaded there_ 2 2 SOl SYSTEM LOADING CP M SOl determines which operating system IS in use_ The system is loaded in the CP M Control Program for Micro processors mode_ NAIf I ll F F F F I RJ M l I fH I MZ 3500 Main CPU logical address during...

Page 11: ...ROM MAIN CPU RAM BANK MA2 SELECT MAl IIAO FFFF COOO BFFF 0 0 0 0 0 0 0 1 lA 3 2 0 0 0 0 0 0 I I 0 0 0 0 1 1 0 I 0 I I I 4000 3FFF 1 0101 2000 IFFF IROMcl IRON IROMII II OM21 11 010131 IROM41 RONA 0000 1102 MOl MOO o o o o o o 1 of track 0 of the floppy disk it loads the IOCS and bootstrap routine to the sub CPU 3 The bootstrap program IS loaded next 4 The bootstrap program determines memory alloca...

Page 12: ...I a IFFF 0000 ROM N02 0 BANK 10101 0 SELECT 10100 0 RAMB 0 0 0 I 0 IROMlllROMzl IkO 31 IkOM41 o I o o I o I o 1 Bank select MAO MA3 is effective for memory area COOOH FFFFH 2 Bank select MOO M02 is effective for memory area 2000H 3F FFH Operational description The state of the system is determined by the bootstrap program before the load of the system program 11 MZ 3500 SUB CPU I 1mB RAN se M ROMS...

Page 13: ...ON r l t O I V flH1 AM I m i2KH I 1 I d AN I ITl 32K I r I i V H AN I101111111 I r U I 2 lO _ _ 1 L ______ J I I 3 KH OW 1111 11 F l0 400 12 r 14 Lol r 12 rN fl 11 41 ur rOM 11 11 I I l il 2 JI L jl EN CU TOM 11 I l J 2C 2L 1 C ljJl tZ or 14 Lulnr I SlO R 2 51 11 F le 765 RAM nr ROM 8KB I r 11 11 1 WllNm 8258 i J I nklVI R I r l I 1 llfoR I Rfolfol U J K IqgOl RS 232L IIf 11 DRIVER IRECEIVFR r I J...

Page 14: ...usses main CPU I O port select and addressing_ The address output from the main CPU is decoded in the 74LS138 to create the select signal Table below describes address map and signal functions IOAB MEMORY MAPPER 74LSI38 Signal name Description NOT USE NOT USE SFD nterface FDC chip select SFOC UPD765 AD used for AD and WA A1 IS don care _ 10SF SFD onterface I O port and DMAC chip select Interrupt s...

Page 15: ...escription F Output signal to set the flipflop to apply interrupt INTO to the main CPU Enables communication between CPU s 8251 510 chip select Io ASO is used for data control selection AS1 AS2 and A53 are don t care 8253 counter chip select A50 and ASl are used for programming during write AS2 and A53 are don t care 8255 PlO chip select ASO and AS1 are used for port control selection AS2 and A53 ...

Page 16: ...RFSH Rn WR DATA BUS 00 07 C PORT LOGIC 7 r WAil TIMING GENERATOR CLK TO RESET SIGNAL MA3 l MA2 MAl O OUT MAO FE M02 MOl MOO 4 SR S Jo OUT MSI O FO MSO STATE SWITCHING SRQl OUT FC El r O IN FE FROM 011 SW F03 F02 FDI JI IN SROY 00 7 L SACK FF INP2 INPI INPO INTB 19 ST SRES SUB CPU RESET SUB CPU SRQB BUS REOUEST SUB CPU SRDY READY SUB CPU ACKNOWLEDGE 1 El INTERRUPT PRIORITY ENCORDER MZ3 O RmflPL RAM...

Page 17: ...U addresssignal A13 A15 merged in the memory mappmg logiC CirCUit to produce 18 AR15 AR 13 AR 15 This is means by which the 4 basic and CP M memory maps are made along With MS 1 and MSO BASIC interpreter 32KB mask ROM chip select signal 19 R32 OUT Valid when SD2 is active Sharp ROM based BASIC Command LOA 02H OUT 3F D ROM 32K select Internal MMR I O port select logic signal 20 10AB IN Goes low by ...

Page 18: ...t from Floppy Interrupt Input from the sub CPU 11nterrupt from No 0 Interrupt Input from slot 1 or 2 I nterrupt from No 1 2 Memory request signal from the main CPU Memory Request Write Signal from the maon CPU Write Interrupt Input from slot 3 or 4 I nterrupt from No 3 4 Input from the FOO Floppy Disk Drive assignment dip switch A 110 1 See the dip sw tch deSCription provided separately Section Gr...

Page 19: ...nal for 8KB area allocated to slot 1 Valid when SD2 is active ROM based BASIC and SD3 RAM based BASIC ROM 1 Ground 5V supply Select signal for 8KB area allocated to slot 2 or 3 Valid when SD2 is active ROM based BASIC and SD3 RAM based BASIC ROM2 3 Read signal from the main CPU Read EAIT signal generation clock Clae Select signal for 8KB area allocated to slot 4 Valid when SD2 or SD3 RAM based BAS...

Page 20: ...re input output signals and rest of others are processed in the lSI 1 I O port output of MEl and ME2 uses the memory at the addresses ME2 8000 BFFF ME1 4000 7FFF When MEl and ME2 are in high state RSAB RASA IS inhibited during memory addresses in RAM A that correspond to overlayed addresses for ME 1 and ME2 This is not true during SDl mode Ml3 OO SRO Bus request from the marn CPU to the sub CPU Su...

Page 21: ...B 4B are enabled by sub CPU_ If A13 th ru A15 were to be at low level the output YO of the LS139 becomes low level so that the output 3Y of the LS147 or CE of the ROM IPL should be at low level Should SRD SMRO be at low lebel as well the output 2Y of the LS157 or OE of the ROM IPL turnde to low lebel to read the ROM IPL Though the sub CPU can access an address range of 0000 to 1FFF theoretIcal Iy ...

Page 22: ...rge Merge of chracters and graphiCS Background calor Control of two Independent screens Control channel number Light pen Input option 8 colors progra T1mable for each character 640 x 400 dots B W one frame Calor deSignation for each character 640 x 400 dots BIW lhree frames Color deSignation pOSSible for each character Calor one frame Merge any graphiC screen 1 to 3 frames Merge a character screen...

Page 23: ...Calor Option 114SKB designation t By character By dot Option 11 196KB t By dot Small letter descenders 0 0 X X Line creation 0 X X X Olsplay memory 3KB 32KB 3KB 32KB 11 96KBIII 3KB 16KB 3KB 4SKB BaSIc 1 frame No frame 1 frame No frame 1 frame 1 page No frame 1 frame 11 pagel No frame Frames OPtIOn I 48KBI 1 frame t 1 frame t 3 frames t 1 frame Option 1I196KBI t 3 frames t 1 frame t 6 frames 2 fram...

Page 24: ...ot 640 dot r r 400 dot 200 dot 1 1 Dot pitch Dot pilch HOrizontal vertical 1 HOrizontal vertical 1 2 3 Color deSignation Eight colors are usable white yellow cyan green violet red blue black Color deSignation 640 x 400 dot 640 x 200 dot ASCII By character By character B ar By dot rap Cs 96Kbyte Bydot By dot Backg ou ld color 8 colols for de 9natlon 2 7 M 3500 W Wh e Three baSIC colors 41 Attribute...

Page 25: ...the VRAM DISplays on CRTl the red elements contaJned In the VRAM Displays on CRTl the green elements contaJned In the VRAM Displays on CRT2 the blue elements contaJned In the VRAM Displays on CRT2 the red elements contaJned In the VRAM Displays on CRT2 the green elements contained In the VRAM I Choice of background color display Color mode Border calor mode In effect Defines the data sIZe for the ...

Page 26: ...2 dots pattern for 1 x 16 elements 8 Element structure character structure and line 0 71 o o o 0 o 0 o 0 o 0 00000 00000 o 0 o 0 o 0 o 0 I 5 100 I 2 Address Oat a _ 1000 00 1001 10 1002 10 1003 28 1004 28 1005 44 1006 44 1007 7C 1008 7C 1009 44 l00A 44 1008 44 10OC 44 1000 00 100E 00 _ 100F 00 Element structure character structure and line line area Character pattern area X Area where pattern and ...

Page 27: ...played for the medium resolution CRT 640 x 200 dot It is possible to display line on the high resolution CRT compatible to line the utilIZIng program of the Model 3200 2 20 line display mode 8 20 20 16 IQ With line HL On 18th raster VL Line to the right of element e V L does not JOin In the case of graphic symbol dISplay VL IS overlaid 10 the pattern 4 2 Video RAM 1 Structure of VRAM GDCl for char...

Page 28: ...ll and can be accessed by 3 Structure of character VRAM 1 When read write from GDC 07FF lA 8 2KX8 2Kx4 ASC I I Attribute 0000 8bit 4bit DO 0 D7 D8 I I 2 During display 07FF lA 8 2Kx8 2KX4 0000 12b t refreshing during the display period_ Number of characters that can be read write within one raster in any mode_ lA B I ASC I I 8b t I I 12blt DO DJ D2 D3 D4 D5 D6 I I I m DO Dl D2 D3 l 8lank Reversp G...

Page 29: ...ode Option I 48K byte 8bit structure Option 1I 96K byte 16b t structure Low High byte byte BFFFO l G I I 0000 I I I I I I 4000 I 0000 J l K BFFF L r J 8bi t 8bi t G 8000 1 1 R 4 0001 ___ 1 B 0000 RAM A 2 1 5 QII I QH 1 SI 1 RASA RAS A14 A15 0000 3FFF RASB RAS A14 A15 4000 7FF F RASe RAS A 14 A 15 8000 BFF F Display mode A14 and A15 are not valid and RASA R ASB RASe are selected together By the DBI...

Page 30: ...ignated for 16 Ch ch8racler B 16bi t 16b t B W 3 frames Col or 1 frame R G 16bi t 16bi t i1 X Y I W IISK 2 GOC 1 80 digits GOC 2 graphic t Oot clock lOO 2XCCLK Hortzontal display time HFP f HS HBP Vertical display time f VFP VS VBP Total rasters 261 rasters Display raster 200 rasters Character display 40 digits 8 bits 16 bits 116MHz 16MHz 16MHz 8MHzl 4MHz 4MHz 2MHz 2MHz 40 15 7 1s 14 Chr 10l s 61 ...

Page 31: ...00 dots 6 Dot clock 19 66MHz 7 Timing Ii Neg lI vt Vlck O P O ltlve 47 8 u 325 21 I m J 024rn vs Negatlvt u U 12r1l 05m I o l il im VFP 11 rasters 0 5rns VS 5 rasters O 24ms VBP 25 rasters 1 2rns 8_ Output rnethod HS VS and VIDEO are indpendent outputs_ 19 66MHz 50 86ns 9 83MHz 101 92ns 4 9152MHz 203 45ns 2 4575MHz 106 9nsl 5 Chr_ tREF O 6ms tR EF 1 23ms 9 HS VS and VIDEO signals are supplied fror...

Page 32: ...s map for 200 rasters CRTC block diagram D splay addre10S 1 Da a Bus CAT Controller IS M2K I k I 2t 1 1 I Control Attrlbule A I J l 4 GDC1I 1 k 1 Hr I i fO I llCO ii 3q I I It C Cl I 0 AI r bu HJd fj et r me rgt C CU 1 Sern 5 0 LSl lCSP 11 I 8B g f C IOf 80 gf f 0 k C3f Rrlatlon twrwppn VRAM 1ddress and crppn lUOO lOO I uu r 1 l r J II 1 3 n n g U 1 B 10 ord 16 bit structure OO 7 tlU IF 31 71 Grap...

Page 33: ......

Page 34: ...ata signal 20 21 GND IN DV supply 22 OSP2 IN Input of display timing signal supplied from the CSP 2 BLlNK signal from the GOC2 is delayed by two flipflop intervals in the CSP 2 to creat this signal 23 VI02 OUT VIDEO output to CRT2 24 LCO OUT Character CG line counter output Becomes address input to the CG when LCO CG address AD 25 ATl IN Attribute data input vertical line B from the 2114A l attrib...

Page 35: ... counter 1 0 I L rL_i nre_S_ig n_a_l_geTn_e_r_a_to_r_ Ih LCI RA400 ClI 25 20 L _ _ _ B VL 1 C3 R HL r L _____ tiLe 4 eK D F F H Yl r CK eK lBLNK 40 80 digit shift circuit HSYO CK D F F __ DF F DF F i CK D F F Cursor erase circuit CSR 2D rc c r V RAM2 CD g u E 08 1_6 g e 0 0 Cl RA4 o 68 5 Border J B2 background tJ f eolor R2 merge CIrCUIt V t O 2 FA12 C R 2 I l Cl t 40 ...

Page 36: ... from CDC3 Used to create L2 LOAn FIASA tlASC CAS FS DBIA DBIC DSP2 in CSP 2 14 AS3 IN Address bus input from the sub CPU AS3 AB3 15 NWRO IN Chip select OUT 5X of the 1 0 port in CSP 2 16 17 DSO DSl IN Data bus input from the sub CPU DSO DBO DSl DBll 18 RA40 IN The signal that goes to high level input from CSP l when the 400 raster CRT s connected Used for clock frequency selection in CSP 2J 19 M4...

Page 37: ...e th s sIgnal GraphIc D RAM CAS COLUMN ADDRESS SELECT s gnal Line address seleclton 5V supply S RAM CG control 51gnal generator Cl L III ill V r PR t f t I 5 I i GDC 2 r u lm811 f t charltCter 0_ display clock f t generator V 32Mllz r OO Rester Lt Clock select L t 5 f t GDC2 3032 1llz Cif CUlt L t graphic dlsplav 400 Rester 200 400 ii clock rasters generator co r r Cl co CK er II j 0 V 00 1 F F IJ...

Page 38: ...reference signal of RAS When at high level used as the timing Signal by which the address Signal is latched Row Address Strobe 7 DRO OUT DMA request output which is connected with the DRO input of the DMA controller is output by the NO USE following two commands 1 DREOE DMA request write CPU memory to image memory 2 DREOR DMA request read Image memory to CPU memory It will be continuously output u...

Page 39: ...e following functions based on the operational mode of the GDC graphic display mode ATlITl O character display mode 1 NK CLC 1 Graphic display mode Image memory address output 2 Character display mode 1 line counter output 3 Character display mode 0 Attribute blinking timing signal and external IlOe counter clear Signal Address 16 line Count 3 Attribute Blink Clear lire Counter 39 A17 CSR I OUT Pr...

Page 40: ...n use only the hIgh order 8 bytes of 16 bytes are set to low level ASCII character structure of the 200 raster CRT ASCII character structure of the 400 raster CRT CircuIt descrtptlon Purpose The character genrerator CG Incorporates all character code used by the 200 raster VIdeo display unIt of the YX 3500 and by the 400 raster Video display unit of the YX 3500 The CG address select ClfrlJlt IS th...

Page 41: ... CH48 0 40 digit CH48 1 80 digit GDC 2 graphic Without VRAM PW8 GDCl character GDC 1 is the master 8 blt structure 0816 01 GDCl GDCl 48K8 200 raster 16 blt structure 0816 11 GDCl GDC2 Graphic 48 96K 8 400 rasters The master GDC must be set as indicated above Oprational example If It was set to 80 digit 16 bit word mode SRES will be o when CH48 1 0816 1 when not in the reset condi tion These signal...

Page 42: ...ibute 03 ARIO DAS Low when 2114 IKx4 I l0400 07FF 1 040 Latter half of ARII CE attribute 07 Low when vi 0000 07FF LS245 0000 GCharacter R W 07FF H SG Display period Perood that the G DC is enabled to read wrote L o FF o FF H SYNC 11 and draw graph le data 116 2K 8 A La 1 11 BLA iK Latter half of attribute Forsl half Circuit description With respect to GCD1 the assignment during read write of the c...

Page 43: ...del 3500_ Set GDC command code Set parameter for the command Set parameter for the command 1 Read write via lhel6 byte FIFO 2 Read write of V RAM in the DMA mode without intervention of the FIFO Outline of the read write data via the FIFCi Method used to give a command to the GDC Command must be given to the GDC in the same rn1nnf r On next page is the program of the above flowchart 48 ...

Page 44: ...data C reg 60H graphic GDe lOH character GDC F I FO Empty COMMAND GDC Return if parameter not sent RET FIFO Empty PARAMETER GDC Return when all parameters were sent MZ3500 Example to display a dot on the fourth bit of the address 0027 CSRW C 49H COMMAND CODE Pl 01H Low order one byte of the ab V RAM 16 bit structure 49 WRITE VECTE P2 OOH P3 30H C 23H C 6CH solute address High order one bytp of tf ...

Page 45: ...LD HL 5000H LD HL 49H 5000 49 H INC L 5001 01 H CSRW data LD HL 01 H 5002 00 H INC L 5003 30 H LD HL 00 H 5004 23 H WRITE data INC L 5005 6CH VECTE data LD HL 30H INC L LD HL 23H INC L LD HL 6CH I LD C 60H C 60H port address during graphic draw LD B 4H B Byte size CSRW data LD HL 5000H HL Top address of the CSRW data I CALL GDC Command par meter of CSRW GDC I LD C 60H LD B 1 H B Byte size of the W...

Page 46: ...T C 78H PI FF Kind of Itne solid line P2 FF VECTW C 4 CH PI OAH Drawing direction P2 78H P3 02H IL X I P4 88H P5 I Il 2 I Y I I X I P6 lOB P7 FBH 2 I 6Y 1 2 lLiX I P8 oOH pg oOH 2 IL Y I WRITE C 23H VECTE C 6CH Explanation Specify the kind of line by TEXTW using C for command code and P for parameter and specify the Itne drawing direction using VECTW and above four values using X and Y The rest wi...

Page 47: ...uch 4 Write protect notch I Q 0 Different write protects are adopted depending on the drive unit used Example 1 In the case of the CE331 the presence of light reflection is sensed by the photo coupler and decoded as wrtte protect Write protected Floppy disk nomenclature Floppy disks called by different names dependng on the manufacturer Floppy media or simply as medl1 Diskette l Floppy disk 2 Type...

Page 48: ...c D c C clock D data o D c o o or double frequency DF Clock and data are written on the media which requires that a clock bit that precede the data o D c D c Waveforms of data written or read in the FM mode are shown below Write data WO Write current Residual magnetic flux on the media Read waveform 14 4pS 1 c D C J C 0 9 I I I D C D C D C D 0 0 0 Wrote Re d Differentiate waveform r I Shaped wavef...

Page 49: ...edes The clock pulse e will be eliminated In above illustra tlon as there IS no data preceding or follOWing the clock Because the data rate is 2Jls for thiS method It IS possible to obtain tWice the density of the FM method 4Jls 6 Media recording format Media is formatted according to the IBM format For Double side media data is written on the front Side head 1 and the reverse side head OO Tracks ...

Page 50: ... Described next IS the procedure to write data on the FO 1 The head IS moved over the track to be written 2 The head IS loaded 3 ID section IS read and repeated until the deSired section IS reached 4 When the deSIred ID section IS found data IS written on that area OATA AM IS also written 5 The data thus written IS now checked If It was written correctly read after write The respective ID section ...

Page 51: ...ve select circuit Motor on circuit 1 I 1 10 x14 I NIlU H SEEK l LCT DIR FAR Sn p q I L _ lJl IoCTIO l snp RW SEEK J Select P 2S FLT T V I lliHITE PHOTH T v TRK WDATA WRITE 11 i WWTITTEEO AAnTA P E CrOMP I PS PSI 9 J 0 7 n TE r AfE WE L J MFM WI SDOW f l I VFO 1 r 1 READ DATA RDATA l L ___ WCLKI4 8MHz r500 KHz WClK I IMHz select circuit I SEL SELl SEL2 SEL3 _ OTOF ON 56 ...

Page 52: ...cs l O INDEX SYNC I f TWDl INT LE M RDATA Vcc Eltl WINDOW GND Ijr n GND WCLK 51 Uf U T DJ R tl Ht TtP RESET Reset MFM MFM Mode RD Read SIDE Side Select WR Write USO 1 Unit Select CS Chip Select WDATA Write Data AO AO PSO 1 Pre Shift DBO 7 Data Bus FLT Fault DRQ DMA Request TRKO Track 0 DACK DMA Acknowledge WPRT Write Protected TC Terminal Count 2 SIDE Two Side INDEX Index READY Ready INT Interrupt...

Page 53: ...It permits readIng operation When 0 it prohibits readIng operation 0 Signal used to discriminate the read write SIgnal from the seek SIgnal that used for drive unit interfacing signal When 0 it indicates RW When 1 It ind cates 0 Signal used to load the read write head 0 Signal used to select head 0 and head 1 for the double slded floppy dISk drive unit When 0 it selects head O When 1 It selects he...

Page 54: ... from the above illustration bit density of the MFM recording method is twice the FM recording method In other words data density of the MFM recording method doubles that of the FM recording method For the 5 6 1 0 port in the MFD interface I O port used in the MF D interface is as follows Lr BUS I O IOMF F9 AO OUT DACK D7 ME D6 SCTRL D5 TC D4 OUT TRIG D3 SEL3 rmIF F8 AO D2 EL2 Dl SELl 0 SELO 2 M O...

Page 55: ...lue 1110 E will be set to the LS163 so that the output is issued 125ns earier than not changed The OB output however will be supplied for a period of two clock cycles 5 8 Media detection Insertion of a media on the MFD is detected via the signal INDEX from the MFD Since it takes 200ms for the media to make a full turn NO MEDIA is detected signal INDEX does not appear within 200ms 60 Set the counte...

Page 56: ...ing a single pluse on the floppy disk the waveform show in a appears Shown in b is two pluses of 411s interval 5 10 VFO circuit 1 Purpose Deviation in the peak point is called peak shift Since pluse intervals of the MFD in actual operation are 4115 6115 and 8J 1 s the largest shift takes place when a pluse appears 811s before or after 4J 1 s as shown in c String of data pulses from the FDD n n n _...

Page 57: ...ion is suspended during the SYNC field located before the ID field and data field 3 After suspention the VFO circuit will synchronize with the read data timing is affected by a speed change In the FDDl Fluctuations in an individual bit that may be seen peak shift are ignored VFO circuit s 5 RlAD DATA BA 5 TR Bvl H 8 4 r IA 8 IY SEL RESH 62 Window SEPARATED DATA SEPARATED CLOCK 5V t t 5V Vct INn t ...

Page 58: ...I IJI II M l J lJ MFM Mode MHZ U OAl OSl L Nomal STD CD 0 Eary CD n n 0 Delay CD CD U U 6 c ...

Page 59: ... MZ 3500 FM mode timing chart A 4M B QA C QB L D QC L WINDOW E F L Normal 0 p G I 1 Does not trace 1ps 64 ...

Page 60: ...BLANK MEDIA Boot OS formation 00 See Fig 1 BOOT 00 BOOT 00 BOOT 00 C 5 D9 D4 Cl D7 40 40 00 J co m E5 D6 D3 Fl E2 C8 Cl D9 D7 40 40 D4 400noneside 40 FI a MA N o 0 m 0 rAP FF 34 tracks Area 10th sector IS also a MAP area Area FF for the media of 40 tracks FF l E5 E5 II Cl 0 c 0 m a CD I E5 E5 65 ...

Page 61: ...ansfers INT IOCScapaclty lk 1 otrack 8 sector 78 F 10 18 1F IFF FF I In FFI IFF FF IlLNO I VOlume 1 DIskette Type name 2 4 SH OOClhnl Track No 1 YC DH OOC lInl Error Mep Bad Treck pE OH DD S dncMl d 29 2C 2F30 20 SC For FLOAD command 34 3C SUB I OC 3D FF 7F1 Fd 1 i Fall name 8 bytes Expander All F when ALOAD command IS not on FF No ALOAD command 813 Foie spec f cat on only 131 With operand 3 bytes...

Page 62: ... 127 FFH t I 128 ___ F_F_H __ l Block r n Starting block number directory 129 13 131 151 152 153 otrack 10 sector FFfl 171 I FFIl FFH 8 tH FFH 67 M7 0 O 28 blocks are controlled by one sector OOH 7FH 80H End of link FE H Links to next map and the starting block number J 32 Indicates the byte position from the top of directory ...

Page 63: ...13 14 15 sector 16 sector Track 1 Sector 1 information CP M 0 Drive unit specIfIcat Ion 5 load address Single sided Block No track Front 2 BO BI 3 B2 B3 38 B72 B73 39 B74 B75 2Kx 76 152K 10 15 Start address Represents the L system media r BOOT 1 N o SIDE 20 SUB IOCS Single density front Track 0 Double density other than front Track 0 o Side 0 front Side 1 reverse Nos of data transfers INT I OCS ca...

Page 64: ...r 8253C 5 Programmable Interval T mer 6 2 Data transmission format 7 bit J with parity I I I I y J _________y y n_ Start bIt Data bIt 7 bIts Panty bIt Stop b t 1 or 2 bits 7 bit J without parity I I I I I I I I y yr Start bIt Data b t 7 b ts Stop bit 8 bit with parity J v _ __y__ ___y_ Start bIt Data b t 8 bIts Parity bit Stop bit 1 or 2 bits 8 bit without parity I I I I I I I v y Start bit Data b...

Page 65: ...uter SW7 Causes on error when the Polarity is inverted PO signal is high during data output 6 5 8251AC controls There are two control words for the 8251 AC 1 Mode instruction Defining general operational para meters such as unit stop bit etc 2 Command instruction Defining status words used for actual operation such as send receive enable etc 1 Definition of generation operational parameters Baud r...

Page 66: ...8251AC Set counter 20Oms Output data to 8251AC Set counter 400ms 73 8251 AC L o HTS COUNT DOWN N ERRORIOI MZ3500 The 8251 send data when C fS goes low The 8251AC would not output unleSS goes low Therefore the state of will be checked when the buffer becomes empty N ERROR 101 ...

Page 67: ... of the receIve command Command InstructIon RXEN DTR TXEN 8251AC WaIts for NMI by the RXRDY sIgnal 8251 AC Resets error by set In DTR hIgh y Command Instruction E R 825IAC ERROR Set counter N N 74 8251 AC Error reset Data Input dIsable 8251AC Data tnput enabled Data output enabled echo back selected L DTR DOWN y ERROR ...

Page 68: ...ut PO Peripheral SW7 0N Causes an error if set high during data output SW7 0F F Causes an error if set low during data output 6 7 Description of LSI s 1 UPD8251AC Programmable Communication Interface The UPD8251A is a USART Universal Synchronous Asynchronous Receiver Transmitter that was specifical ly designed for data communication The USART receives parallel data from the CPU and converts it int...

Page 69: ...d for a wide range of microcomputer system timing control Features Z 80 compatible Three sets of 16 bit counters DC 4MHz of count rate Programmable SIX operational modes and timer duration Choice of binary counter BCD counter N channel MOS input output TTL compatible Single 5V supply 24 pin DIP Intel 8253 5 compatible Pm configuration Top View D7 D6 D5 D4 D3 D2 DI DO CLKO OUTO GATEO GND 1 2 4 5 6 ...

Page 70: ... SUB INTR L FROM MAIN INT TO SUB FROM KEY STK L IN IN OUT IN OUT OUT J C N C IN IN OUT IN N C IN IN OUT IN IN OUT IN IN OUT 2 45MHz clock DATA SET READY DATA TERMINAL READY CLEAR TO SEND REQUEST TO SEND TRANSMITTER DATA TRANSMITTER CLOCK RECEIVE DATA RECEIVER READY RECEIVE CLOCK 2 45MHz Vcc To TXC RXC of the 8251 2 45MHz From OUT2 MUSIC 2 45MHz Vcc To GATE 1 INTO H L H 1 READY CS MZ 3500 PO MPER S...

Page 71: ...e GND Above pin numbers are of the mOOel 3500 malO unit Pin No S gnal name IN OUT Function 1 SiROEl PRINTER Data is transfered to prtnter when STROB is h gh 3 DATA 1 5 DATA 2 7 DATA 3 9 DATA 4 PRINTER Data output to the printer 11 DATA 5 13 DATA 6 15 DATA 7 17 DATA 8 19 ACK PRINTER Indicates the end of character put or function input I 21 BUSY PRINTER When high It enables to receive data 23 PE PRI...

Page 72: ...r key processing and RS232C Input the ACK signal is latched by means of the OBF pin function 7 4_ Data transfer timing BUSY ACK OBF 8255 PC 7 DATA STROBE l s 1 1_ MIN l s MIN PRINTER MZ 1P02 MZ 1P03 CE 330P 331P 332P Broken line in the above figure represents timing for the CE 330P and 331P For detail of timing refer to Manual provided with printer 7 5 General description of control software Set t...

Page 73: ... INPUT PORT 74LS244 DS7 74LS244 DS6 port address Ol00 xxxx DS5 Us4J IN X DS3 OUT 4 DS2 DSI DSO Output OBF output ACK input J INTR Output HLT KEY STK DK PUTR J PE BUSY I ATA8 l DATA7 IlATA6 I ATA5 llATA4 DATA3 DATA2 DATAl ACK r SET ACK STROBE MU SIC sustain NOT USE Printer ACKC STC DC PiM SRDY CLK Keyboard D10 C2 Cl CO STRB Keyboard Printer CG selectIon Sub CPU READY Clock Reads the 8255 OBF PC7 ou...

Page 74: ... Rl tl 8 OTHER INTERFACES l l f q v v A r 17 IOK 11 0 IOR Er D 8 1 I 6 4 J r 1 I 8 r 1 0 l 1 2t bo 128 127 VCC 6 B 56 0 r S DR I I g 0 l S L0 L 8 0 IF OR 11 10 PlI 82 S 22 RP l v g g 8 9 20 2 22 2 2 f fif fi J JC 2 18 5 4 l 5 2 B 0 IF g I c LS244 v 0 N r Z C jlPD1990AC II x N r 0 HI I t 32 t i L Vcc TE T PIN I F Ir SHIFT mode SHIFT mode SHIFT mode SHIFT mode 81 7 S HOLD HOLD mode ...

Page 75: ...Hz 0 0 1 Register shift Data input output LSB Output of LSB 0 1 0 Time set Data of the 40 bit SIR is LSB Output preset to the time counter 0 1 1 Time read Data in the time cou nter LSB Output is read to the 4O bit S R Input output format Data Shift Not possible PosSIble Not possible Not possible Example In the case of 10 o clock 25 minutes 49 seconds July 30th 8 I HrJ fl Note Data retention Shifts...

Page 76: ...cuit Music output waveform Tonal signal OUT1 Sustain PC4 2SC458 emitter 2SC458 collector Speaker output GETEl Vcc 1 1 8253 C C 7 C T c 0 C l 0 t V to VOICE n n n r r r 0 to CLOCK GENERATER 2 45076 MHz 83 MZ SOO jl PD8255 13 SPKR ...

Page 77: ...mte lP03 lP04 Color injket printer CE 330P 80 character printer 333P 136 character printer 331M Optional MFD drive unit 330X Plotter MZ 1F02 Optional MFD drive unit lF03 Optional MFD drive unit single deck lR03 Graphic board lR05 2 Expansion unit Signal assignment by slot M CPU bus line OL SFD CONTR VOl DRAM control sig 32K mask RO CE nal M BAS I C 8K mask RO ROM RO RO RO M I M2 M3 M4 Tt T2 3 lNT ...

Page 78: ...ec mal pOint 52 pin of MMR A comma s outputted for a dec mal pOint Low state or open ER Signal dUring data output w II result In an error ToCTS OSR The Signal ER becomes invalid of the 8251 CO IS high as long as power IS on to the malO unit CD goes h gh only dUring data output However t would not go high f the echo back function s on the host s de An error IS cause when the PO Signal s high dUring...

Page 79: ... MZ3530 PC3541 ON OFF OFF ON ON ON machines that use the double sided mlnlfloppy disk drive MZ3540 V lr l1 OFF OFF ON ON ON ON Switches are set In this manner when the SH is used for the optou al MFD ON OFF ON ON ON ON SWitches are set in this manner when the OH is used for the optional MFD OFF ON ON ON ON ON Test mode 1 ON ON ON ON ON ON Test mode 2 X X OFF OFF OFF Individual CPU PWB test Can be ...

Page 80: ...When an overcurrent is met in the 5V 12V circuit it causes to increase the voltage at both ends of the over current detector resistor R1 which in turn causes to increase the 03 collector current for there arises larger voltage difference between the emitter and base of the 07 transistor 03 This makes the gate voltage of the thyns tor increased owing to activation of SR WitL Jctlvation of SR it mak...

Page 81: ...R5 R6 IQI Oscdlator CirCUIt L2 v Q5 Cl I D3 I _ D2 00 00 J 00 0_ no O cc Cl 1UUUUL 25KHz JUlIlJl Switching regulator and constant voltage control circuit Oscdlator CircUli VR IS the 5V or 12V adjusting YR 25KHz D3 IS provided to discharge current from Cl after power off 88 5V OT 12V 7 52 V 5V or 12 ...

Page 82: ...acitor Cl and the coil L2 The circuit composed of D4 and VRl is the reference voltage for the 5 or l2V supply which is used to control the emitter current flowing to the transistor 09 The current supplied from 09 is used to create Tr3 inactive by the delayed Cl and C2 voltages which supplied from Trl R2 VR1 D3 It goes high with deactivation of Tr3 3 Alarm circuit Alarm generation circuit G n 1 Ra ...

Page 83: ...nction with the CTRL key DEFIB DEF10B DEF1B DBF10B 6 Handling of functional symbols and graphic symbols See the code table 7 Use of the CTRL key to discriminate RUN and CONT of the DEB key Push the DEB in conjunction with the CTRL key to start running 8 Handling of special codes COpy command CTRL DJ ten key ESCape CTRL ICMD BRK CTRL ICONTI 9 PRO OP Sent to the CPU after power on and when PRO OP is...

Page 84: ... cycle n n n n n n RETURN DATA OUT I rl lj4 Two key entry Key 1 tt Key 2 STROBE Jl n n n n n n IL 5_5ms 5ms H 5ms tt 15ms U 15ms H 5ms_ n n n n AET n n n DATA 1 I OUT DATA 2 OUT 10 3 Key serial transmission procedure 1 Data format Key CPU 27 26 25 24 23 22 21 2 DATA Parity All nine bits Command CPU Key All 4 bits Parity 91 ...

Page 85: ... controller accepts it Unless the ACK signal was detected the same data is sent again assuming a transmission error DCK STCK 12 5 JL5 SUB CPU Case when the error data link sub CPU not enable to receive data properly is established 1 When parity error is found after the check sum test 2 When the sub CPU is in execution of the NMI routine or when NMI is applied during data tr m f jj 3 When an error ...

Page 86: ...oller basic flow Power ON Read key status and initialize Check internal ROM Timer START ISmS Key serch N Check program Key Buff PRO OP LOAD Code convert ASC11 G F Code convert SEND TO SUB CPU 93 MZ3500 N y Reset CTRL mode ...

Page 87: ... P17 33 and 34 are not used 35 P24 IN Not used 36 P25 Keyboard type Identifier plO Keyboard type IS Identified by mears of KSO KS1 KS2 of KUCl IN 38 P27 an KUS2 whether It IS GNO or Ne 39 T1 IN Acknowledge Input from the CPU ACKIC Sent only when the CPU receives 8 correct data 40 V CC IN 5V supply 11 SELF CHECK FUNCTIONS The 3500 performs self eheck test dunng mltlal program loadmg of the ROM 11 t...

Page 88: ... start executing the test Procedure 1 Set dip switches on of the 4 bit unit located in middle of the front side of the board as illustrated at the right r No 2 OFF ON l Set dip switches on of the 2 bit unit located on the front side of the board 3 Insert the media into a slot of any diskette drive unit 4 Turn the power on 5 Load the program from the specified track and sector to start execution of...

Page 89: ...pushing the HALT siwtch to start the test program Then push the HALT switch to step to each test phase Result of GO NO GO will appears on the video screen except for the CRT interface and speaker tests No of data transfers INT IOes capacity l Kl 1 Sub IOes can be divided into eight blocks If divided to less than eight blocks the block following to the final block mut be traced by FFH Procedurel 1 ...

Page 90: ...s on the display screen of 40 digits and 20 lines Test No 2 Confirm all patterns on the display screen of 80 digits and 25 lines Test No 3 1 Confirm that an entire screen is Filled with H 2 Confirm that attributes are shown as illustrated 97 MZ JSCC 2 VRAM check Proceed to test for ASCII and atflbute f RAM Display During test penode display shows under following 1 Display rev Iced U for entire scr...

Page 91: ...erface signal lines and action of the 8255 are tested Dispaly 1 Normal test ending PR OK 2 Abnormal test ending PR ER 61 light pen interface test Performance of light pen interface signal lines and the action of the GDC are tested Display On the upper left corner of the screen is displayed character and line 11 Normal test ending LP OK 2 Abnormal test ending LP ER 7 RS232C interface test Performan...

Page 92: ... 8 ROM IPL MAIN CPU CHECKER FLOW CHART 1 2 MAINCUP CHECKERS TART NOTE Indudes SEEK errOf and RECAlI8RANTE NOTE Includes SEEK error and AECAliBRATE 99 MZS500 ...

Page 93: ... MZ3500 MAIN CPU CHECKER FLOW CHART 1 2 N Add up all data In the ROM SUM 0 7 y Option RAM read write check Change bank of the option RAM N HALT N y y 100 J HALT ...

Page 94: ...SUB CPU CHECKER FLOW CHART 1 sue CPU CHECKER S1ART 101 ...

Page 95: ...on with the DEB in depres sion it goes into the keyboard self test mode 2 Depress key in a given sequence If key is depressed in a correct sequence it makes the alpha symbol LOCK LED activated each time a key is pushed If the key was pushed in a wrong sequence or when a failure is met in the key it makes the LED blinked It returns to the normal mode upon completion of testing all keys With this th...

Page 96: ...IOes input outout control program ROM NO SYSTEM MEDIA code transfM 103 Contents of parameter sector 1 Kind of MFO Single side doubte iencrty or double side doubh denclty 2 Track and sector where loes IS stored LoarJr 1r and truch Number of sectors Note The sub loader IS contamed In the leading sector AOM based JUMP TO ROM BASIC To OOOOH cod vansfee ...

Page 97: ...LOAD IOes SEEK READ Transfer the IOes program to shared RAM BOOOH FBOOH LOAD BOOT LOAD BOOT SSEK READ JUMP BOOT ADDRESS NO SEEK READ ERROR ERROR BOOT Program used to start the system Position of boostrap program on the media Sector 2 thru 5 of Track O ERROR 104 BOOTERROR on disp HALT CPU STOP ...

Page 98: ... 122 SUB CPU IPL FLOW CHART POWER ON SUS CPU IPL JUMP SUB toes HALT eUPSTOP SYSTEM MEDIA M The malo CPU will perform retr als unl j the n n media 11 Inserted 105 Z 3500 ...

Page 99: ...ON RF2 Sy BUSAK lN f ZZr INTB CAS OFF CPU sw PI SW ITOB INTO ROMA S Lt T t37 SWI O _ SW2 ROIIB PR INTER Srlect yJS SRDY 2 t SRDY RöiiC i L o SW2 ON OFF O _ S W3 Lsa6 Ij l _ SACK 31 SACK ROM I 6K HA b SW3 j lR t n OO öI ler 1 1 SW4 W4 R SP Il 22 2 O W4 65 NR 6 I l iA BlIS O Ol ROJR 6 L _ _ _ _ _ _ _ _ _ _ ____________ tR BlIS W5ko SW5A TRI BUS R04 H 07 6 8Knx I l LO K S C 16 SW6 RS 23 1 ITIBJr 38 1...

Page 100: ...o JO K h Ioon V r L J Vec Mv c 7 5 9 I 103 IOKfl NM1 STW 5 22Kn 3 4 22Kn L 3aK INT SOO Ve c 33K X6r r Vcc n 50 l 8 Je 11 V r TtR I IIUSAK pc ____ Vec 2 4576Mllz 7406 p IKu cc HL SRQ SI R Z 2Kf I IE I 8 TiiR jl r k J I 5 r r f I r I 71 1I o I 7 I 1 0 1 s SVr5H _ 1 1 I I 11 i I L 47f1 OI JlJCO 1 C2Hillc l K l U 1 I c r L 6 I 2 l 2C 1 l eL I Vec I I r t 1 I 1 I ll IOR r ii i Eö S iH V SW6 h j I i i 1...

Page 101: ...SUB CPU CSR 9 L 51121 L o AT BLNK LI _38 S WR Söif HSYNC 100il 1II 3 JllIl1JLlrn 12 If A4 A5 A6A7 A8 A9 AlM 11 13J 910 11 I I I 2 1AI2 Wk OllT 10 AO I BK by tt M f 1 L csfL r AI 12E 1000 1i 3 3KIt A2 Cha racter Genera tor öE b Nl lI WR 1 S05 NSYIB NABC 2 I c 1 10011 CSI r ASO O EOOII AS 1 1 1 4 AS I AS I Vee I j 11 2 I I I AS2 11 6 AS2 ARellEF 11 3 3KIl I C4 I OJ IOOfl 3 1k H I S 166 11 E CII I JS...

Page 102: ... 8____________________________ 11 LS166 IG LOAD 27B n 020 2M Sl20 2 6 AL t t j i O 16 28 R __________________________ 7 04 vr 158 ll ________t ____ LSOO I sf 7H 8 J v C JJ1U JJ f 2ll l I 7404 LSOO 10 2 0 CL J J ICL LS278 l i1 Cl M rils 8 21 s YCK CKl llICK 11 12 Q 2P 4 D 3 119 6 10 19 112 1 11 112 ll I r t r r r 1 A T Ill 1 ADB AnIS AniS 01 ADI8 ADI2 oll 010 AD9 All NYT IAnS IA06 IArM IA03 I 1 2 1...

Page 103: ...SET AIO I l L 1 JA l2 OB7 CPU 0 o rIRES ET A O I 2KX8 1 ABIS rTI 1AO 2KX8 REOUEST o f IBUSRQ STATlC STATIC SUB CPU SW4B 00 D7 00 07 READY 1 IS CK SUB CPU 1 _ 1 IBUSACK ili ACKNOWlEDGE MT OBO S lli DISP SW r FOS FROM I I t Ri5 I F02 S 7 jr 1 WR r I IN Bl5A fE IORQ 1 1 INTR SROY MREQ 7 7 RFSH WAIT 00 7 FF RD SACK TFff BUSRQ I T WAIT Ii TIMING 1 LS244 _ VAIT _ 11 IGENERATOF NMI RXRDY 8251AC 8253C 5 8...

Page 104: ...DATA5 12 I 11 SEL3 12 GND 6 GND Vi Vee 7 Vee WAIT 7 BUSAK 13 DATAS 14 1 G 13 GND 7 GND Vee 8 Vee RFSH 8 BUSRQ 15 DATA7 IS NL 15 MOTOR ON IS 8 Vee 14 Vee VOICE 9 VOICE GND INT2 9 INTI 17 DATA8 18 D 17 DIRECTION 18 TWI ST DSO 9 DSI PAIR INTFD 10 SYSRES ROM4 10 RF2 19 ACK 20 A 19 STEP 20 DS2 10 DS3 RO 11 WR CAS 11 RASD 21 BUSY 22 I 21 WR DATA 22 G DS4 11 DS5 I IORQ 12 MREQ ROM3 12 RASC 23 PE 24 23 WR...

Page 105: ...OICE G INT2 9 INT r l r 20 G 19 STEP 20 G 19 STEP SYSRES io INTFD INT4 10 CAS INTFD 10 SYSRES ROM4 10 RF2 22 N 2r WR DATA 22 N 21 WR DATA WR 11 RD INT2 11 MPX RD 11 WR CAS il RASD 24 D 2 WR GATE 24 D 23 WR GATE MREQ 12 IORQ INTl 12 RASB I IORQ 12 MREQ ROM3 12 RASC I 26 25 TRACKO 26 25 TRACKO D6 13 D7 RASD 13 ROMD DO 13 Dl ROM2 13 RASB 28 WR PR 28 WR PR D4 4 D5 RASC 14 ROMC D2 14 D3 ROMD 14 ROMI 30...

Page 106: ...14 LS 03 4A 3B 3A 3Y IG IAl tv lA Y3 IA3 Y 1A 4 2V G 74 LS 139 lA IB IY 2A 2 2Y G IJ 74 LS 04 IAI H lA yS lA n lA VI SELE T DATA OUTPUTS 74 LS 14 74LS2415 6Y 5 5Y 4 V lA IY 2A Y 1Y c m 14 LS OB A 3H W lA IY 2A 3Y ND GND 74lS1S7 74 I S 213 l pUT OUTf T XrrpUT TkOBF 4Y SA SH SY lA IY 2A 2H 2Y 74 LS 10 le IY 3C 1B 3A 3Y IIJ 2Q IJ t Il l 8 2Y ll 11 l l T t Tf Ll I H I I Il r lA 2A B n 2Y 1 1 18 ...

Page 107: ...S IQ IV et 3 J D iJ l 74L5B6 I ll III 19 74LS93 r Htll ROt M VU L L 7406 lA IY 2A Y aY GND 545157 I yrr PUTS lA 18 IV 21 28 2Y G D I OUTPUT I PUTS 5188 OUT PUT I IPUTS 75189 TC40498P L J PD1990C l l I LO 11 L Ill IJ TA7313 9 17 2 I 3 f _ I I PA3 PA2 PAl PAO AI 9 I LHOO80 P08255 I D5 116 r V 1 1 7 1 l6 1 115 1 114 I ...

Page 108: ... 11 AI4 21 fin 31 ILK 41 RIl 2 no 12 13 22 hlIfP 32 RFTB 42 Tf31l 3 01 13 A I 23 hOAH 3 l k 2H la lT41l 4 02 14 R 24 flOHIl 34 III TIl H L 5 03 15 RU 2 hUL B 35 lL l1l 45 n 6 04 16 ARI3 26 I R 1l 36 IT 1l 46 D 7 D5 17 R I 4 27 I J I B 37 I rOB 47 1 8 1 6 18 h l I 2k I BB lh TTTR 48 2 I I 14 I I _ l I J I J I I 4 1_ l _Lh_ I J_ honlso 1 l 11 I 10 20 51 3 61 ll 71 I S2 4 62 11 72 1 11 53 Il 63 02 B ...

Page 109: ... MZ 3500 PARTS GUIDE LIST ...

Page 110: ... supply Unit for IOOV series 18 GCABBIOO4ACZZ BG N 0 Top cabmet 19 GCOVHIOOIACZZ AM N D Slot cover 20 LANGTI003ACZZ AX N C F xlnR anRle for MFO 21 LANGT 1 0 1 OACZZ AE C F xmg angle for fan 22 LCHSM1008ACZZ AY C ChassIs 23 LX LZ6023RCZZ AA C Rivet 24 NFANPIOOIACZZ BM N B Fan motor 25 RMEMRIOO2ACZZ N E MFD Unit 26 GLEGPOOIOUCZZ AB C Rubber foot 27 XBPSD30P08KSO AA C Screw 28 XBPSD40P06KSO AA C Scre...

Page 111: ...9Z if 91 O I 6 l i lE i qrl L OOSE ZW ...

Page 112: ...RIOO4ACZZ AC N D Cover for I O slot 15 LHLDZIOOIACZZ AD N C GUide for PWB l 16 QCNW IOO3ACZZ AK N C Connector for light pen 17 QCNW IOO4ACZZ AM N C Connector for k y board 18 QCNW I047ACZZ AM N C Connector for CRT I 19 QCNW I044ACZZ AM N C Connector for CRT 2 20 XBBSC26P04000 AA C Screw 21 XBBSC30P06000 AA C Screw 22 XBPSD30P06KSO AA C Screw 23 XUPSD26P06000 AA C Screw 24 LANGQIOO4ACZZ AH N C Conn...

Page 113: ...NW I047ACZZ 19 QCNW lO44ACZZ 20 QC NW 1 0 0 4 A C Z Z 21 QCNW IOO3ACZZ 26 LHLDF6648RCZZ I i j e 9 16 PRICE RANK AW AT AZ AQ AX AK AC AC AA AC AB AC AF AM AM AM AK AB 4 NEW MARK N N N N N _ o I 2 PART RANK C C C C C C C C C C C C C C C C C C Connector Connector Connector Connector Connector Connector Connector Connector Connector Connector Connector Connector Connector Connector for CRT 2 Connector...

Page 114: ...resistor 33KOX8 1 8W IO 28 UBATNIOOIACZZ AS N A Battery 29 VCCSPUIHLIOOO AA C CapaCitor 50V 10PF 30 VCCSPUIHL330J AA C Ca paCltor 50WV 33PF 31 VCCSPUIHL470J AA C CapaCltor_i50V 47PF 32 VCEAAAICWI06Q AB C Capacitor l6WV 10 F 33 VCEAAAICWI07M AB C Capacitor l6WV 100uF 34 VCEAAAICW336M AB C CapaCitor 16WV 33pF 35 VCEAAA I EWI 06M AB C Capacitor 25WV 10 F 36 VCEAAAIEWI07M AC C CapaCitor 25WV 100pFl 37...

Page 115: ...ReSistor l 4W 68KO 5 1 106 VRD SU2EYI52J AA C ReSistor l 4W 1 5KO J 107 VRD SU2EY470J AA C ReSistor 470l J08 VRD SU2EY681J AA C ReSistor l 4W 6800 J 109 VRD SU2EY821J AA C ReSistor l 4W 8200 5 110 VRD SU2EY822J AA C ReSistor l 4W 82KO 5 III VS2SC458KC l AD B TranSistor 112 X8PSD30P06KSO AA C Screw 113 X8PSD30P08000 AA C Screw I QJ Power supply unit NO PARTS CODE PRICE NEW PART DESCRIPTION RANK MAR...

Page 116: ...30 M C025 62 OAE30 170008 AG N C Capacitor 25UL8330 MJ C026 63 OAE30213525 AG N C Capacitor 35UL8220 M CO2 64 OA 30195258 AG N C Capacitor 25UL8220 M C02S 65 OAE30120524 AC N C Capacitor 50F2S223K C029 66 OAE30120524 AC N C Capacitor 50F2S223K C030 67 OAE30164409 AC N C Capacitor 50F2S332K C031 68 OAE30116729 AK N C Resistorr TM10K PV8 8 2KOl RVOO1 69 OAE30116729 AK N C Resistorr TMIOK PV8 8 2KO R...

Page 117: ... 9J 05 Key unit MZl K02 1 K03 1 K04 1 K 11 MZ 3500 i 1 16 1 r 18 ...

Page 118: ... IC 22 VHIM74LS273 1 AP B LC 23 VH M74LS367 I AH B IC 24 VHIM74LS373 1 AQ B IC 25 VHISN7404 I AE B IC 26 VHIUPD7220D I BS B LSI 27 VRD ST2EYIOIJ AA C ReSistor l 2W 1000 28 VRD ST2EYI03J AA I C ReSistor 1 2W IOKO 29 VRD ST2EY331J AA C ReSistor l 2W 3300 30 VRD ST2EY332J AA C ReSistor l 2W 3 3KOJ 31 VRD SU2EY470J AA C ReSistor l 2W 470 32 VRS PT3DB680K AB C ReSistor 2W 680 33 VS2SA673 DI I AC B Tran...

Page 119: ...2005SCZZ 8 7 AA C LANGSI006ACZZ 2 2 AF N C QPWBF 100 5ACZZ 1 7 AA N C LANGTIOOIACZZ 9 10 AG C QSOCZ6414ACZZ 5 12 AD C LANGTI002ACZZ 9 IS AC C QSOCZ6416ACZZ 5 13 AD C LANGTI003ACZZ 1 20 AX N C If 10 7 AD C LANGTI008ACZZ 10 6 AF N C If 11 6 AD C LANGTIOIOACZZ 1 21 AE C QSDCZ6424ACZZ 5 14 AE C LBNDJOO09FCZZ Il l AC D QSOCZ6428ACZZ 5 IS AE C LCHSMI 0 0 8ACZZ 1 22 AY C QSOCZ6440ACZZ 5 16 AG C LHLDF6648...

Page 120: ...r 1 8 2 4i A B B 1 9 121 AD B ER E5 1 1 0 Jtt A C B VH D 8 7 49H A C 0 5 9 1Z5 SII t N l B I Ih PARTS CODE VH HM4 721 14 1 VH HM6116P3 1 VH LH0080A I VH M5K4116P Z VH MS 8 7 2 5 P I 5 VH M74LSOO I 1 VH M74LS02 1 VH M74LS03 1 VH M7HS04 I VH M74LS08 1 11 VH M7HSIO I 1 VH M74LS125 1 VH M74LSI26 I VH M74LS138 1 VH M74LSI39 I VH M74LSI4 1 VH M74LSI57 I 1 1 VH M74LS161 1 VH M74LS163 1 VH M74LSI66 I VH M...

Page 121: ...BTSC40P06000 1 31 AA C IJ 9 129 AA C XBTSD30P04000 10 34 AA C VRD STHY272J 6 85 AA N C XBTSF40P08000 1 32 AA C VRD ST2EY33IJ 5 93 AA C XCPSD40P12000 1 33 AA C IJ 5 101 AA C XNESD30 24000 2 31 AA C IJ 6 83 AA N C IJ 2 33 AA C IJ 6 89 AA N C 8 59 AA C IJ 6 99 AA N C XUPSC26P06000 9 21 AA C IJ 6 100 AA N C XUPSC30P08000 9 22 AA C IJ 6 106 AA N C XUPSD26P06000 2 23 AA C IJ 8 46 AA C 0 J IJ 10 29 AA C ...

Page 122: ...5Y2K56000 9 40 AH N C OAEJOI69653 6 45 AC N C OOP85Y2K60000 9 41 AH N C If 6 54 AD N C If 6 55 AD N C OAEJOI70008 6 61 AG N C If 6 62 AG N C OAE30195258 6 64 AG N C OAEJ 0 2 0 0 7 74 6 30 AG N B If 6 31 AG N B OAE30213525 6 63 AG N C OAEJ0216904 6 I AS N B OAEJ0221517 6 7 Al N B OAEJ0221520 6 8 AH N B OAEJ0221546 6 18 AH N B oAEJ 0 2 2 7 2 36 6 46 AD N C OAE30250326 6 33 AG N B OAE30258784 6 6 AX ...

Page 123: ...SHARP SHARP CORPORATION Industrial Instruments Group Reliability Quality Control Department Yamatokoriyama Nara 639 11 Japan 1983 January Printed In Japan s ...