Sharp MZ-80B, Owner'S Manual

Page 1: ...Personal Computer IIIZ OOODU OWNER S MANUAL SHARP ...

Page 2: ...SHARP Personal Computer MZ 808 Owner s Manual September 1981 080211 010981 Printed in Japan SHARP CORPORATION ...

Page 3: ...olors of the wires in the power cable of this device may not correspond with the colored markings identifying the terminals in your plug proceed as follows The blue colored wire must be connected to the terminal which is marked with the letter N or colored black The brown colored wire must be connected to the terminal which is marked with the letter L or colored red ii ...

Page 4: ...general operating procedures read these chapters first Chapter 3 and 4 describe the hardware This information will be helpful to you if you intend to expand system All software is supplied in the form of files A cassette tape which contains the SB 5510 BASIC interpreter and MONITOR SB 151 0 which support the standard BASIC programming language is included with the MZ 80B Refer to the BASIC Languag...

Page 5: ...tely Observe the following guidelines to keep your set in optimum operating condition Do not place the MZ 80B in locations where the temperature is extremely high or low or where it varies to a great extent Avoid exposing the unit to direct sunlight vibration or dust Handle the power cable carefully to prevent it from being damaged When removing it from the AC outlet turn the power off first then ...

Page 6: ...m Loader 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 2 0 2 Keyboard 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 5 2 0 2 0 1 Main keyboard 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 6 2 0 2 0 2 Numeric pad 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 2 0 2 0 3 Speci...

Page 7: ... state Memory map for normal state 42 43 4 2 3 Memory map for V RAM accessing state 44 4 3 Signal system for the 8255 block the 8253 block and the IPO block 48 4 3 1 Signal system for the 8255 block 49 4 3 2 Signal system for the 8253 block 51 4 3 3 Signal system for the Z80A PIO block 52 4 4 The MZ 80B circuit diagrams 56 APPENDIX 69 A l Z80A CPU technical data 70 A 2 Z80A PIO technical data 108 ...

Page 8: ...uch as BASIC PASCAL FORTRAN and COBOL Computers operate measuring systems and automatic control systems in a variety of plants and networks In laboratories engaged in software development the computer is even used to study itself What can your MZ 80B do There is no definite answer to this question since the MZ 80B can be used in such a wide range ofapplications You may apply it to any purpose you ...

Page 9: ...emory and any type of system software can be loaded into it from an external file This makes it possible to make the best possible use of the main memory area The 1 0 devices timer initial program loader etc support the CPU and main memory The initial program loader is automatically started when the power switch of the MZ 80B is turned on It loads programs from a cassette tape or diskette file the...

Page 10: ... it In the MZ 80B the IPL Initial Program Loader automatically loads programs which are stored on cassette tape or if a disk drive is connected diskette into the main memory when the power is turned on then transfers control to the program loaded Initial program loading from cassette tape is com pleted in a few minutes loading from a diskette is accomplished in seconds The IPL is stored in ROM Rea...

Page 11: ...ters are normally input from the console of the MZ 80B by pressing the SHIFT Ikey A command is provided however which makes it possible to reverse the shift function so that capital letters are input when the SHIFT Ikey is pressed Tabulation settings can also be made by the program These functions improve the efficiency of message coding and table and graph editing The cursor control keys allow th...

Page 12: ...ble in the past Manual operation keys REW D sToP and EJEcT are provided on the console The MZ 80B has a superior display system with the following features it displays all characters and patterns input from the keyboard in any mode it operates in either the 40 or 80 characters line mode the scrolling area can be restricted to a part of the screen and black and white can be reversed Further 2 optio...

Page 13: ...floppy disk drive uses a double density mini floppy diskette 286K bytes disket te with a diameter of 5 25 inches both sides of which are used for recording It enables use of the DISK BASIC inter Pret r which is suitable for practical business applications of the double precision DISK BASIC interpreter which performs 16 digit BCD operations Thus the expanded system ex hibits an ability which is com...

Page 14: ...AM I RAM _ 1 Graph 8KB I 32KB v I I V RAM V RAM UNIVERSAL rt PTR PTP RAM Charact 2KB Graph 8KB 1 0 etc 32KB r I i I MODEM RS 232C t1TELETYPEWRIT BOOT ROM l L 1 etc 2KB 1 r I ER IEEE 488 I IEEE 488 standar INTERFACE T devices CPU 7 EXT SYSTEM BUS I I Z80A 1 v PORT I I t PRINTER I t INTERFACE PRINTER I d I FD FLOPPY I r INTERFACE DISK KEY BOARD I I I MCR II MARK CARD I Vt I INTERFACE SOUND rv CASSET...

Page 15: ......

Page 16: ... This chapter describes the constituent units ofthe MZ 808 and their functions Locations of constituent units Use and function of the Initial Program Loader Functions of keys on the keyboard Outline of display control systems 9 ...

Page 17: ... Cassette tape compartment Name plate Special function keys i Cursor control keys FIGURE 2 1 Rear view of the MZ SOB Brightness con FIGURE 2 2 L o 1 Cassette deck control keys 4 lr t Numeric pad Frame ground 1 0 module acce s window No 1 6 ...

Page 18: ...load the cassette tape recorder with the corresponding cassette before turning on the MZ 80B to activate sys tem software stored in a diskette file the corresponding diskette must be placed in drive No 1 of the floppy disk unit connected to the MZ 80B before the power is turned on 2 1 1 Activating system software contained in a cassette tape file Load the cassette tape into the cassette tape recor...

Page 19: ...e master diskette in drive No I energize the MZ 80B The MZ 80B loads the system software automatically After a few seconds a message should appear indicating that DISK BASIC interpreter SB 651 0 has been activated A special method of loading system programs from a ROM card connected to the expansion I 0 port is possible The IPL of the MZ 80B enables system program loading in this manner when the I...

Page 20: ...nitial Program Loading Execution of Initial Pro gram Loading normally progresses as indicated by the solid line however manual operations may be required depending upon conditions at the branchpoints I Power SW ON I I IPL Reset SW ON I I I t C Key No a Yes FD Connection No FD Power SW OFF ON Diskette setting No Yes I SET READY FOR FD SET READY FOR CMT l I f SELECT CMT OR FD No Tape setting C key C...

Page 21: ...ding first initiate cassette based loading then press the BREAK key This will cause loading control to move to branch point 3 causing the tape to be rewound When the tape is completely rewound press the 0 key Pressing the 0 key before the tape is completely rewound causes the system to begin the file search immediately When you must fast forward the tape first initiate cassette based loading then ...

Page 22: ...keyboard typewriter keyboard conforms to ASCII standards and includes character keys and control keys such as the carriage return key and the break key The numeric pad is for entering numeric data and is similar to that of an ordinary electronic calculator The ten blue keys in the upper left are keys whose functions are defined by the user The four yellow keys in the upper center are cursor contro...

Page 23: ...R KEYS ITJ GJCD CTI FIGURE 2 8 Main keyboard and its control keys Three operation modes are as follows 1 Normal mode 2 Graphic mode 3 Reverse mode Some of these keys produce different characters according to operation mode as shown in Figure 2 9 Except under special circumstances characters input from the main keyboard are dis played on the screen in the position where cursor is located reverse mo...

Page 24: ... all following characters of the string to the right one space DEL delete INST insert Shift lock key When this key is pressed with the I SHIFT Ikey depressed the SHIFT Ikey is locked When the I SHIFT Ikey is locked lsFT LocKIlamp lights Press ing this key again without pressing the SHIFT Ikey releases the shift lock SFT LOCK shift lock With this key depressed the character keys which have graphic ...

Page 25: ...he screen so most people prefer to write their programs in capital letters When a key has two non alphabetic symbols on it such as I above the 0 key See Figure 2 10 pressing the key alone enters 8 If you hold down the SHIFT j key while pressing I will be entered Only the 26 letter keys are shifted in the opposite direction from a standard typewriter t The sh LOcK key locks the SHIFT key so that it...

Page 26: ...y key other than one of these 30 keys is pressed the character assigned to the key is input Note that graphic patterns cannot be input when the SHIFT key is held down Included in the graphic patterns are ruled line patterns which are provided for generating tables Figure 2 12 shows an example of a table generated using ruled line patterns FIGURE 2 12 A table generated in the graphic mode These gra...

Page 27: ...ase character and pressing it with the I SHIFT key depressed inputs the reverse lower case character The reverse characters and symbols correspond to ASCII codes AOH to FEH See Figure A l ASCII code table As shown in Figure 2 21 the dot patterns constituting reverse characters are set reset in the exact opposite state of those comprising normal characters FIGURE 2 14 A title generated in the rever...

Page 28: ...KEYS FIGURE 2 15 Location of number pad TAPE CONTROL When the Ioo key is pressed once two zeros are entered just as if the 0 key were pressed twice A small projection is provided on the face of the 0 key so that the operator can enter numeric data without constantly looking at the keyboard All of the keys on the numeric pad operate without relation to the main keyboard operation mode or the I SHIF...

Page 29: ... 1 RUN Once this statement is executed special function key 1 performs the function of the RUN com mand until it is redefined Thus when special function key I is pressed in the direct mode the follow ing appears on the display Then by pressing CR key the RUN command is executed The c R key can be defined together with the RUN command as the function of a special function key if desired Execute DEF...

Page 30: ...Figure 2 17 is displayed KLIST I LIST 2 RUN 3 RUN lOOt 4 AUTO y 5 CONT1t 6 2 7182818 7 3 1415927 8 Personal Computer MZ 80B 9 10 KLIST Ready FIGURE 2 17 List of special function keys This list shows that special function keys I through 5 are defined as commands plus the I c R key special function keys 6 through 8 are defined as data special function key 9 is undefined and special function key 10 i...

Page 31: ... position every time a cursor control key is pressed Therefore to move the cursor to the right 3 positions the key must be pressed three times To move the cursor repetitively hold down the SHIFT key and press the appropriate cursor control key The cursor will then move continuously until either of these keys is released When the cursor is to be moved to a position nearer to the upper left corner o...

Page 32: ...sette tape EJEcT Ejects the cassette These functions have no relation to the mode in which the computer is operating Recording and reading data to from the cassette tape are controlled by the software With BASIC SB 551 0 recording or reading of program text is performed by the SAVE and LOAD commands respectively Recording or reading of data files is performed by the PRINT T and INPUT T statements ...

Page 33: ... 1 F through 1r FF can be displayed on the CRT screen t Input of these characters from the keyboard was explained previously Characters en tered are displayed at the position where the cursor is located The cursor pointer is controlled by the monitor program The cursor position is changed by one of control codes 01 06 See ASCII code table FIGURE 2 22 FIGURE 2 20 shows forms in which the character ...

Page 34: ...u L 0 1 0 1 2 3 4 5 6 7 8 9 A B c D E F 2 3 4 5 6 7 8 9 A B c FIGURE 2 21 All characters along with corresponding ASCII Code Note U L Upper 4 bits Lower 4 bits 27 D E F ...

Page 35: ...28 UPPER 4 BITS 0 I 2 3 4 56 7 8 9 ABC DE F FIGURE 2 22 ASCII Codes of characters and control codes ...

Page 36: ... 2 3 2 Graphic display control system FIGURE 2 23 shows an example of a projection of a three dimensional object displayed using BASIC graphic control statements Refer to BASIC Language Manual FIGURE 2 23 ...

Page 37: ......

Page 38: ... Module 32K byte RAM card Graphic Memory 1 8K byte RAM card Expansion 1 0 Port These optional devices must be installed properly according to procedures explained in this chapter Other optional devices are connected via the expansion I 0 port General procedures and notes on connecting optional devices via the expansion I 0 port are contained in the last part of this chapter 31 ...

Page 39: ...B Optional devices which can be installed in the main cabinet of the MZ 80B are expansion memory module MZ 80RM graphic memory I MZ 80GM and expansion 1 0 port MZ 80EU FIGURE 3 1 shows the locations in which these devices are installed MZ 80RM MZ 80EU MZ 80GM FIGURE 3 1 ...

Page 40: ...side of the main cabinet See FIGURE 3 2 Retaining screw FIGURE 3 2 L Retaining screw Gently lift the upper part of the main cabinet and support it with the supporting arm See FIG URE 3 3 Supporting arm FIGURE 3 3 CAUTION If the power is turned on with the upper part of the main cabinet lifted electrical parts may be damaged Metal articles remaining in the cabinet can cause serious trouble Ensure t...

Page 41: ...ear side of the CPU board as viewed from the rear The standard 32K byte RAM card is already installed beside the expansion RAM connector The connector pins on the bottom of the expansion RAM card can be inserted into the 20 pin connector on the CPU board The connector cannot be inserted backwards Visually check orientation of the expansion RAM card before inserting it See FIGURE 3 4 FIGURE 3 4 ...

Page 42: ...ce facing downward and the flat cable output port facing the front See FIGURE 3 5 FIGURE3 5 After affixing the graphic memory 1 card connect the wide 40 wire flat cable connector to termi nal CNS on the CPU board with the 6 markings aligned Then connect the narrow 10 pin flat cable connector to terminal CN13 Do not mistake CN4 located beside CNS for CNS CN4 is for connecting the expansion I 0 port...

Page 43: ...the two screws holding the window cover panel as shown above 3 Affix the expansion I 0 port on the inside with two screws as shown above 2 Insert the expansion I 0 port MZ 80EU as shown above 4 Affix the expansion I 0 board at the window with two screws as shown above FIGURE 3 7 After the expansion 1 0 port is installed connect the 40 wire flat cable connector to terminal CN4 of the CPU board and ...

Page 44: ...etting the Graphic Memory 2 Card Lift the upper cabinet and set the cabinet support arm Insert the MZ 80GMK in position No 4 located in the upper right hand corner as viewed from the rear of the expansion I 0 port as shown in FIGURE 3 8 FIGURE 3 8 Then connect the 10 wire flat cable connector of the MZ 80GMK to terminal CN2 of graphic memory 1 card MZ 80GM See FIGURE 3 9 10 wire flat cable FIGURE ...

Page 45: ...view of the expansion 1 0 port access window The graphic memory 2 card MZ 80GMK is already set in position No 4 For details on setting 1 0 interfaces for the floppy disk drive printer and color display device refer to their respective manuals FIGURE 3 10 ...

Page 46: ...r units of the MZ 808 and the following diagrams Standard system configuration Memory configurations 8255 signal system 8253 signal system PIO signal system All circuit diagrams These materials are for reference only and the Sharp Corporation is not obligated to answer any questions about them 39 ...

Page 47: ...OWER SWITCH c 1 II POWER UNIT I SV POWER 12V SV ONIPL GROUND RESET l R E ____ s E J T A I Z80A A CPU I A I I CRYSTAL 4MHz 16 OSCILLA MHz1_ TOR 31 25kHz JL L E D Main Memory RAM 32k bytes IPL 1 ROM 2k bytes I L r RAM 32k bytes OPTION ADDRESS SELECTOR r I J L I 1111 I ADDRESS BUS II 11 11 HA HI IS I J il_ CONTROL BUS r HAND SHAKE Z80A PIO PORTS I i 1 KEYBOARD FIGURE4 1 ...

Page 48: ...DEO GENE c V RAM T RATOR GRAPHIC I J 0 rt 111 8k bytes v OPTION I I II II II I II I II V RAM II II p GRAPHIC II II E 8k bytes ADDRESS BUS R OPTION I II r t p H _ E 0 DATA BUS R p II A T L I CONTR L Rl S I 0 I v I N 0 7 p 0 8255 8253 R co C1 C2 T r uu 1 sec 12 h CASSETTE TAPE CASSETTE TAPE DECK 1 0 DECK The MZ 80B System Diagram No 1 I No 6 41 ...

Page 49: ...ap for IPL operation Program File Boot ROM addresses range from 0000 to 07FF This IPL loads a system program for example BASIC interpreter PASCAL or Assembler to the head of RAM I the standard 32k byte package In this state the RAM I addresses range from 8000 to FFFF After loading the addresses are inverted from the IPL state to the normal state so that the system program is activated When the IPL...

Page 50: ...sion area FFFF FIGURE 4 3 Memory map for the normal state In the case of the 32k bytes standard RAM addresses range from 0000 to 7FFF in the case of the 64k bytes full RAM the address space consists of the full area from 0000 to FFFF When addresses are changed from the IPL state to the normal state or vice versa the operation is controlled by output terminal signals cl c3 of port c of the 8255 as ...

Page 51: ...ted by A7 of PIO When two pages of graphic V RAM are used selection of graphic pages I and II is made by OUT port F4 This operation is shown in FIGURE 4 4 Address 0000 7FFF 8000 CFFF DOOO DFFF EOOO RAM I RAM IT Option RAM IT RAM IT Addr Addr Switching by PIO A I Addr I V RAM ddr Character Switching by OUT port F4 Addr Addr FFFFL_________ V RAM Graphic I Option V RAM Graphic IT Option Page 1 Page 2...

Page 52: ... state That is the following instructions are executed IN A E8H SET 6 A SET 7 A OUT E8H A This address switching is shown in FIGURE 4 5 Address 0000 o RAMI Switching by PIO A6 5000 5FFF 6000 7FFF 8000 RAM I RAM I RAM II Option FFFF V RAM Character r V RAM Graphic I Addr Option Page 1 Switching by OUT port F4 V RAM Graphic II Option Page 2 FIGURE 4 5 Switching of main memory and V RAM 2 ...

Page 53: ...igure V RAM characters and graphic I and ll can be displayed simultaneously The relation between V RAM addresses and corresponding positions on the CRT display is as shown in FIGURE 4 7 V RAM characters DOOO D027 DODO 5000 5027 5000 25 lines 25 lines D3CO D3E7 D780 53CO 53E7 5780 40 characters 80 characters V RAM graphic NOTE 200 dots EOOO 6000 FF18 7Fl8 320 dots E027 6027 FF3F 7F3F The addresses ...

Page 54: ...ut 00 0 X X 01 X X 0 02 0 0 X 03 X 0 0 oc 0 X X OD X X 0 OE 0 0 X OF X 0 0 Note Input 0 V RAM transfer enabled X V RAM transfer disabled Output 0 shown on CRT display X not shown on CRT display Output X X X X 0 0 0 0 If 03H is delivered to port F4 with OlH stored in EOOO then OlH is transferred to V RAM G ll EOOO but is not displayed on the CRT because the display indicator is set at V RAM G 1 ...

Page 55: ...put output ports is shown below together with a summary of the service modes of the port of each controller Table 4 2 CPU s Input Output port Controller Service mode of each port EO PA output El PB input 8255 E2 Pc output E3 mode control E4 Co mode 2 16 bit rate generator E5 8253 cl mode 2 16 bit rate generator E6 Cz mode 2 16 bit rate generator E7 mode control E8 A output mode 3 bit control E9 mo...

Page 56: ...oard LEDs FIGURE 4 8 summarizes the signal system for the 8255 Keyboard RVS LED GRPH SFT LOCK 8255 PA7 Cassette deck control PA6 PA D7 8 PA4 I STOP PA3 Do PLAY PA2 FF REW ready PA MOTOR ON PA0 A Write data PC7 Ao RD WR PC6 FF REW latch PC5 EJECT PC4 RD PC3 WR PC2 Read data PC RESET Set ready t PC0 Pawl provided not r cs provided PB7 PB6 PB 5 Display sound control PB4 __ PB3 10 PB2 REVERSE 10 PB Re...

Page 57: ...PB7 H Detects break key during cassette play PB6 Input terminal for cassette data PBs L Indicates tape is set in the cassette deck PB4 L Applies pawl to prohibit writing cassette tape PB3 Reserved PB2 PB 1 PB0 H Indicates fly back between frame displays Port C Port terminal Active Control function PC 7 Outputs data to be written into cassette PC6 H Sets head amp to READ state WRITE with L PCs H La...

Page 58: ...Hz input pulses and delivers a pulse to OUT 0 every second counter 1 counts the output pulses of counter 0 and delivers a pulse to OUT 1 every 12 hours counter 2 counts the output pulses of counter 1 and switches between 0 and 1 to work as an AM PM flag See FIGURE 4 9 8253 OUT2 Counter GATE2 2 CLK2 12 hours OUT I 8 D Counter GATE I I 7 1 Do CLK I 1 second OUTO Counter GATEO 0 CLKO 31 25 kHz FIGURE...

Page 59: ...r mode selection control signal FIGURE 4 1 0 summarizes the signal system for the Z80A PIO Key data input terminal 8 ports Port B handshake r I r t Key strobe output terminal 12 ports PortA handshake R SEL V RAM AD SEL V RAM AD SEL 40CHR 80C R HR r 154 1 PIO D B I 8 B Do B B B B A SEL B B C D SEL Bo B ROY B STB IORQ RD A A CE A Ml A A A A Ao ARDY lEI vlf 11 A STB lEO INT 4 5V GND r r i FIGURE 4 10...

Page 60: ...ses DOOO FFFF to V RAM A6 H Assigns addresses 50000 7FFF to V RAM As H Changes screen to 80 character mode L 40 character mode A4 L Turns all key strobe signals to L A3 11 Output strobe signals for keyboard scan A2 AI Ao Port B Port Active Control function terminal B7 B6 Bs B4 Data inputs for keyboard scan B3 B2 B1 Bo I ...

Page 61: ...d the key data is F7H it indicates that the S key is being pressed Table 4 5 Key scanning strobe signals and bit data E MODE 0 1 2 3 4 5 6 7 F I F2 F3 F4 Fs F6 F7 Fs 0 0 F9 F IO 8 9 00 1 1 0 1 2 3 4 5 6 7 2 1 TAB SPACE icRi ITJ G G I BREAK I 3 a b c d e f g I f A B f c f D T E r F f G R 4 2 f H h I i J j K k I M m n 0 nr f L iF N f 0 PI 5 3 F 0 p p Q q R r s s T t u u v v w f i 11 p I r f w f 6 3 ...

Page 62: ...des used so far are as follows LD A 33H LD I A IM 2 LD HL 5080H LD 3370H HL LD A 70H OUT EBH A LD A CFH OUT EBH A LD A FFH OUT EBH A LD A 97H OUT EBH A LD A 7FH OUT EBH A IN A E8H AND FOH OR 13H OUT E8H A Setting of vector register setting of interrupt mode 2 Setting the address of the interrupt routine in the interrupt address setting the interrupt vector 8 bits Setting port B in mode 3 Setting a...

Page 63: ...ollows I CPU board block 1 CPU signal system 2 CPU board block 2 3 CPU board block 3 8255 and PIO signal system 4 CPU board block 4 RAM signal system 5 CPU board block 5 6 CRT display control 7 Cassette tape deck control 8 Power supply 9 Graphic Memory 1 card optional 10 Expansion 1 0 port optional 11 Graphic Memory 2 card optional ...

Page 64: ... 1 1 L 245 DIR EXWAff A 8 07 p 0 I 0 c ir734 L S74 IC33 IC33 NMl INT EXINT NT EXWAIT 1 IC 17 z 4 _ RFSH LSOS WAIT MREQ1 IORQ 4 RD f 1c 7 L S244 r I RESET I I II j 1 28 1RFSH 19 MREQ L SOO LSOO RESET IORQ R5 VIR Ml 20 IORQ 21 R5 y zz WR IC5 LS04 RAMWR PIO t 4M I 1 I I G J res rc s L 04 LS04 I f 2G J 1c 1 L SOO IC5 LS04 12 fc _ _ l IC5 L S04 27 Ml 18 HALT 26 RESET 06 05 04 03 02 01 Do 1 c s L S244 A...

Page 65: ...58 FIGURE 4 12 CPU board block 2 co 0 co N 2 ...

Page 66: ... 0 i co r u li li Q i i D D II D II I ii11ffi n FIGURE 4 13 CPU board block 3 8255 and PIO signal system r l m 0 m N 2 59 ...

Page 67: ...N I 1 1 1 1 1 1 i r 0 f 1 f f t t f f t 1 fr e 1 f t t f t t t 1 0 N t 1 0 j c 0 i 1 0 0 t 0 1 0 t t 1 1 t t 1 1 t 1 1 1 r r f t t t t t t I t t t 0 t t t t i 1 g f a t 1 0 f t t t 1 FIGURE 4 14 CPU board block 4 RAM signal system ...

Page 68: ...GNO 10 A7 II A6 12 A5 13 A4 14 A3 15 A2 16 AI 17 A0 18 GNO 19 07 20 06 21 05 22 04 23 03 24 02 25 01 26 00 27 GNO 28 NMI 29 EX WAIT 30 EX INT 31 EX RESET 32 RESET 33 lEO 34 HALT 35 MREQ 36 IOREQ 37 RO 38 WR 39 Ml 40 BUS0 5V 12V 5V To MZ SOEU GNO FIGURE 4 15 CPU board block 5 ...

Page 69: ...____ Sound input Sync Video GND E 12V 1 I VS P0090P 16YA R2002 C20n2 500 8 150P RVR 8 0015PA ICONTR AST g l r lml r 02001 02Z7 5A 11 I R20 05 R2001 120 02003 47 R2013 12V 3 31112W gy R2021 1 330 IK QPWBF 0324PAZZ 02006 R g039TA r C2040 4l7 l 50V RTRNF2015TA t 0 N ...

Page 70: ...J 3003 S WHITE 63 CASSETTE CONTROL R3ll6 R311S R3117 A3120 IOKG 2MG 6K G S I2V tSV C3026 100 0 J3006 4 S 12V NS 12V o 4b t I I C3021 IOlZ R302 6 O L L _ __ J3005 7 4 J3005 9 t J300s e C3020 ro sz R3025 NS 12V 0300 tSIUI I 03015 J t 11 Z S8 7 6 ZP L J3005 3l 03020 2587610 03005 ISI885 BRKL J3005 4 J o _J f I J_ J______ J3005 S 1 PNL L J3005 6 J 1 fl iSL J oos CM J3005 2J FIGURE 4 17 Cassette tape d...

Page 71: ... 1 c i c G 00 1 1 0 1 en 0 z 1 10 I I I I y 0 FILTER PWB I I I FlOI I I I CIOI I lil f F 250V l F 250 V I I I I I I I I I T I OI T F 0 ...

Page 72: ...2 IC6 L 157 ICS IC 9 LS I57 LS42 Go J 3 c A12 A Y B ____ 2L I L_ S G A 0 1 19 22231 2 3 4 6 7 9 IC 4 2016 C5 Ato A9 A8A7 Ask A4A3A2At Ao 8 L W E r r r r r r r 1 r r r r r r 1 r r o E Rb o l t t J I 3 1 JC I 2KRAM 201 6 h _JJ j L_ o O _D T n D D D T D ro___________ ICI9 SV J I M o j 12 CK L S08 i N c ol I K Q p GND 0 1 IC 17 L SI07 IC21 LSOO HBLK D 1__ ICI6 L 04 VBLK D FIGURE 4 19 Graphic Memory 1 ...

Page 73: ...8 WR Ml 40 sus RA2 I Kfi x5 De IC2 lEO LS08 12 3 II IC2 LS08 lEO I IEI2 IE02 t CNI CN2 t INTi INT2 A 8 EX INT 5V 5V RAI IK l x4 nfi D I 3 2 IC I 4 0 LS08 w iC2 IC I LS08 LS08 IEJ s IEO s E 4 IE04 lEts lEOs IE 6 IE06 t CN 3 CN4 CN 5 CN6 t t INT3 INT4 INT5 INT6 J CNI v CN6 A I 8 t5V I t5V D2 2 D3 Dl 3 D4 DO 4 D5 GND 5 D6 A15 6 07 Al4 7 BUS Al3 8 Ml Al2 9 WR All 10 RD AIO II IOREQ A9 12 MREQ A8 13 GN...

Page 74: ...r h I p5 Ro IC 14 IC I3 5 L 04 LSOO 19 I IC 8 2KRAM 2016 t _ i r o r o r i r r r r Jl IC 7 i t r _ j 6H QH9 2 OIR G te A 8 Do i 01 4 02 o i 0 04 G 4 F E 0 1 0 o 1 8 9 4 06 07 c CLH eM o QJl V _ _ _ lJf GNOo i l L 5245 ICIS L 32 HIV 3 g J c o _J Go Gt 62 G G G G Gr Go G Goo IMo K Q GNO o 1 IC II l LSI07 IC I3 h t t tt tt LSOO HBLK IC I4 L 04 VBLK O 8 Qo y y A IC 5 IC 6 IC 1 0 L S93 L S93 LS93 R I F...

Page 75: ......

Page 76: ...APPENDIX The Appendix includes technical data on the Z80A CPU and Z80A P O for reference This infor mation will be helpful to you in expanding the system 69 ...

Page 77: ...e also two sets of accumulator and flag registers Special Purpose Registers 1 Program ctmnter PC The program counter holds the 16 bit address of the current instruction being fetched from memory The PC is automatically incremented after its contents have been transferred to the address lines When a program jump occurs the new value is automatically placed in the PC overriding the incrementer 2 Sta...

Page 78: ...ynamically located anywhere in memory with absolute minimal access time to the routine 5 Memory Refresh Register R The Z 80A CPU contains a memory refresh counter to enable dynamic memories to be used with the same ease as static memories Seven bits of this 8 bit register are automatically incremented after each instruction fetch The eighth bit will remain as programmed as the result of an LD R A ...

Page 79: ...errupt or subroutine processing These general purpose registers are used for a wide range of applications by the programmer They also simplify programming especially in ROM based systems where little external read write memory is available 1 2 ARITHMETIC AND LOGIC UNIT ALU The 8 bit arithmetic and logical instructions of the CPU are executed in the ALU Internally the ALU communi cates with the reg...

Page 80: ...d for l 0 device data exchanges 1 0 addressing uses the 8 lower address bits to allow the user to directly select up to 256 input or 256 output ports A0 is the least significant address bit During refresh time the lower 7 bits contain a valid refresh address Tri state input output active high D0 D7 constitute an 8 bit bidirectional data bus The data bus is used for data exchanges with memory and I...

Page 81: ...able or a maskable interrupt with the mask enabled before operation can resume While halted the CPU executes NOP s to maintain memory refresh activity Input active low WAIT indicates to the Z SOA CPU that the addressed memory or I 0 devices are not ready for a data transfer The CPU continues to enter wait states for as long as this signal is active This signal allows memory or 1 0 devices of any s...

Page 82: ...equest the CPU address bus data bus and tri state output control signals to go to a high impedance state so that other devices can control these buses When BUSRQ is activated the CPU will set these buses to a high imped ance state as soon as the current CPU machine cycle is terminated Output active low Bus acknowledge is used to indicate to the requesting device that the CPU address bus data bus a...

Page 83: ...xt section The fetch cycle M 1 is used to fetch the OP code of the next instruction to be executed Subsequent machine cycles move data between the CPU and memory or 1 0 devices and they may have anywhere from three to five T cycles again they may be lengthened by wait states to synchronize the external devices to the CPU The following paragraphs des cribe the timing which occurs within any of the ...

Page 84: ... per formed at this time During T3 and T4 the lower 7 bits of the address bus contain a memory refresh address and the RFSH signal becomes active to indicate that a refresh read of all dynamic memories should be accomplished Notice that a RD sgianl is not generated during refresh time to prevent data from different memory segments from being gated onto the data bus The MREQ signal during refresh t...

Page 85: ...a memory write cycle the MREQ also becomes active when the address bus is stable so that it can be used directly as a chip enable for dynamic memo ries The WR line is active when data on the data bus is stable so that it can be used directly as a R W pulse to virtually any type of semiconductor memory Furthermore the WR signal goes inactive one half T state before the address and data bus contents...

Page 86: ... onto the data bus just as in the case of a memory read For I 0 write operations the WR line is used as a clock to the I 0 port again with sufficient overlap timing automatically provided so that the rising edge may be used as a data clock Figure 3 0 3A illustrates how additional wait states may be added with the WAIT line The operation is identical to that previously described BUS REQUEST ACKNOWL...

Page 87: ... C f r r WAIT I DATA BUS OUT I Write Cyc le Tl AO A7 X IORQ DATA BUS RD DATA BUS WR INPUT OR OUTPUT CYCLES FIGURE 3 0 3 T2 Tw Tw PORT ADDRESS I I r _ __J _ _ OUT I Ta iL I IN I I Automatically inserted WAIT state INPUT OR OUTPUT CYCLES WITH WAIT STATES FIGURE 3 0 3A X READ CYCLE r WRITE CYCLE ...

Page 88: ... special Ml cycle is generated During this special MI cycle the IORQ signal becomes active instead of the normal MREQ to indicate that the interrupting device can place an 8 bit vector on the data bus Notice that two wait states are automatically added to this cycle These states are added so that a ripple priority interrupt scheme can be easily implemented The two wait states allow sufficient time...

Page 89: ...AST M CYCLE OF INSTRUCTION IORQ 74S04 5V IORQ Q TE 1 P_H_E_R AL B WAIT 0 7432 Q T_O_C_P_U_ _ _ 1 MI L J EXTENDING INTERRUPT ACKNOWLEDGE TIME WITH WAIT STATE FIGURE 3 0 5A AUTOMATIC WAIT USER WAIT Tw Tw DATA BUS _ _______________ WAIT NORMAL ACKNOWLEDGE TIME f ACKNOWLEDGE TIME WITH ONE ADDITIONAL WAIT STATE REQUEST ACKNOWLEDGE CYCLE WITH ONE ADDITIONAL WAIT STATE FIGURE 3 0 5B ...

Page 90: ...ed The two interrupt lines are sam pled with the rising clock edge during each T4 state as shown in Figure 3 0 7 If a non maskable interrupt has been received or a maskable interrupt has been received and the interrupt enable flip flop is set then the halt state will be exited on the next rising clock edge The following cycle will then be an interrupt acknowledge cycle corresponding to the type of...

Page 91: ...ck transfer and the block search instructions can be interrupted during their execution so as to not occupy the CPU for long periods of time The arithmetic and logical instructions operate on data stored in the accumulator and other general purpose CPU registers or external memory locations The results of the operations are placed in the accumulator and the appropriate flags are set according to t...

Page 92: ...on set is demonstrated by the fact that the Z 80A CPU can provide all required floppy disk formatting i e the CPU provides the preamble address data and enables the CRC codes on double density floppy disk drives on an interrupt driven basis Finally the basic CPU control instructions allow various options and modes This group includes instructions such as setting or resetting the interrupt enable f...

Page 93: ...om the jump relative OP code address Another major advantage is that it allows for relocatable code Extended Addressing Extended Addressing provides for two bytes 16 bits of address to be included in the instruc tion This data can be an address to which a program can jump or it can be an address where an operand is located f O_P_C_o_d_e_ _ ___________ 1 one or two bytes Low Order Address or Low or...

Page 94: ...f this type of instruction would be to load the accumulator with the data in the memory location pointed to by the HL register contents Indexed addressing is actually a form of register indirect addressing except that a displacement is added with indexed addressing Register indirect addressing allows for very powerful but simple to implement memory accesses The block move and search commands in th...

Page 95: ...c OP code the actual OP code the symbolic operation the content of the flag register following the execution of each instruction the num ber of bytes required for each instruction as well as the number of memory cycles and the total number of T states external clock periods required for the fetching and execution of each instruction Care has been taken to make each table self explanatory without r...

Page 96: ...9 01 110 r d HL n 00 110 110 2 3 10 n IX d n II 011 101 4 5 19 00 110 110 d n IY d n 11 111 101 4 5 19 00 110 110 d n A LlC 00 001 010 I 2 7 A DE 00 011 010 I 2 7 A nn 00 111 010 3 4 13 n n BC A 00 000 010 1 2 7 DE A 00 010 010 I 2 7 nn A 00 110 010 3 4 13 n n A I t 1FF2 t 0 11 101 101 2 2 9 01 010 111 A R t 1FF2 t 0 0 11 101 101 2 2 9 01 011 111 I A II 101 101 2 2 9 01 000 111 R A 11 101 101 2 2 ...

Page 97: ...6 L n n n n LD dd nn ddu nn l 11 101 lOt 4 6 20 dd1 nn 01 ddt 01t n n LD I X nn Xu nn l 11 011 tOt 4 6 20 IX1 nn 00 tot 010 n n LD IY nn IYu nn l 11111 tO I 4 6 20 IY1 nn 00 101 010 n n LD nn HL nn l H 00 100 010 3 5 16 nn L n n LD nn dd nn l dd 11 11 101 101 4 6 20 nn ddL Ot ddO 011 n n LD nn IX nn t IXu 11 011 t01 4 6 20 nn IXL 00 tOO 010 n n LD nn IY nn 1 1Yu 11111 101 4 6 20 nn IYL 00 100 010 ...

Page 98: ...1 IY1 SP 11 100 001 Notes dd is any of the register pairs BC DE HL SP qq is any of the register pairs AF BC DE HL No 1 o Xo of of I ofT Comments Bytes Cycles States I 3 11 qq Pair BC 2 4 15 01 DE 10 HL 2 4 15 11 AF 1 10 2 4 14 2 4 14 PAIR H PAIR L refer to high order and low order eight bits of the register pair respectively E g BCL C AFH A Flag Notation flag not affected 0 flag reset 1 flag set X...

Page 99: ... EX SP IY IYH S P l 11 111 101 2 6 23 JY S P 11 100 011 CD LDI DE HL t 0 0 11 101 101 2 4 16 Load HL int o DE DE D E 1 10 100 000 increment the point e rs and HL HL 1 decr ement t he byte counter BC BC 1 BC LDIR DE HL 0 0 0 11 101 101 2 5 21 If BC O DE DE l 10 110 000 2 4 16 If BC O HL HL 1 BC BC 1 Repeat un t il BC O CD LDD DE HL t 0 0 11 101 101 2 4 16 DE D E 1 10 101 000 HL HL 1 BC BC 1 LDDR DE...

Page 100: ...I I I 1 I 11 101 101 2 4 16 HL HL 1 10 101 001 BC BC 1 CD A HL I I I 1 I 11 101 101 2 5 21 If BC O and A HL HL HL 1 10 111 001 2 4 16 If BC O or A HL BC BC 1 Repeat until A HL or BC O Notes J P V flag is 0 if the result of BC 1 0 otherwise P V 1 Z flag is 1 if A HL otherwise Z 0 Flag Notation flag not affected 0 flag reset 1 flag set X flag is unknown i flag is affected according to the result of ...

Page 101: ...J in the ADD set above XOR s A AVs 0 t p t 0 0 m CP s A s t t v t 1 t ill INC r r r 1 t v t 0 t 00 r 1 1 4 INC HL HL HL l t v t 0 t 00 110 QQ 1 3 11 INC IX d IX d t v t 0 t 11 011 101 3 6 23 IX d l 00 110 QQ d INC IY d IY d t v t 0 t 11 111 101 3 6 23 IY d l 00 110 QQ d DEC m m m 1 t v t 1 t I Q m is any of r HL IX d IY d as shown for INC Same format and st at es as INC Replace ITQQ with l QI in O...

Page 102: ...complement CY CY t 0 X 00 Ill Ill I 1 4 Compl ement carry flag CY I I 0 0 oo no 111 No ope ration 00 000 000 PC PC I CPU halted 01 110 110 IFF 0 II 110011 I FF I II Ill 011 Sst interrupt 11 101 101 mode 0 01 ooo no Set interrupt 11 101 101 mode 1 01 010 110 Set int errupt 11 101 101 mode 2 01 Oil 110 Notes IFF indicates the interrupt enable flip flop CY indicates the carry flip flop I 1 4 Set carr...

Page 103: ...l 101 00 100 011 ss ss 1 00 sst 011 IX IX 1 11 011 101 00 101 011 IY IY 1 11 111 101 00 101 011 Notes ss is any of the register pairs BC DE HL SP pp is any of the register pairs BC DE IX SP rr is any of the register pairs BC DE IY SP o No No of oDI ofT Comments Bytes Cycles States 1 3 11 ss 2 4 15 00 01 2 4 15 10 11 2 4 15 pp 00 01 10 11 2 4 15 rr 00 01 10 11 1 1 6 2 2 10 2 2 10 1 1 6 2 2 10 2 2 1...

Page 104: ...ll 110 000 B t t p t 0 0 11 011 101 4 6 23 001 c s 11 001 011 010 v d 011 E 00 Qill 110 100 H t t p t 0 0 11 111 101 101 L 4 6 23 111 A 11 001 011 d 00 Qill 110 t t p t 0 0 QlQ_ lnst ruction format and st ates s ar e as s hown for RLC m t t p t 0 0 Qm To form new OP code replace QQ of RLC m with shown code t t p t 0 0 ill 0 t l I t 0 0 QQJ s l l p t 0 0 ill 0 t t p l 0 0 ill Rotate digit left and ...

Page 105: ...1 11 111 101 4 5 20 b Bit T ested 11 001 011 000 0 d 001 1 01 b 110 010 2 rb 1 11 001 011 2 2 8 011 3 Til b r 100 4 HLh 1 11 001 011 2 4 15 101 5 110 6 Til b 110 111 7 IX dh 1 11 011 101 4 6 23 11 001 011 d Til b 110 IY dh 1 11 111 101 4 6 23 11 001 011 d Til b 110 s b 0 1 To form new OP code s r HL replace of SET b m IX d with QJ Flags and I ime IY d states for SET instructi on Notes The notation...

Page 106: ... 2 2 1 2 2 2 2 3 3 3 2 3 2 3 2 3 2 3 1 2 2 2 3 10 10 12 7 12 7 12 7 12 7 12 4 8 8 8 Notes e represents the extension in the relative addressing mode e is a signed two s complement number in the range 126 129 e 2 in the op code provides an effective address of pc e as PC is incremented by 2 prior to the addition of e cc 000 001 010 Comments Condition NZnon zero Z zero NCnon carry 011 C carry 100 PO...

Page 107: ...c is false continue otherwise 1 3 11 If cc is true same as RET cc Return from ll 101 101 2 4 14 000 int errupt 01 001 101 001 Return from non ll 101 101 2 4 14 010 maskable interrupt 01 000 101 011 100 101 110 Ill SP l PCII II t 111 1 3 ll t SP 2 PCt 000 P C11 0 001 PC P 010 011 100 101 110 111 Flag Notation flag not affected 0 flag reset 1 flag set X flag is unknown t flag is affected according t...

Page 108: ...01 101 2 5 21 C to Au A B B 1 10 111 010 ifB 0 B to Ax Alc HL HL 1 2 4 16 Repeat until B O If B o n A 11 010 011 2 3 11 n to Au A Ace to Ax Al C r II 101 101 2 3 12 C to An A 01 r 001 B to Ax Ala CD C HL t X X 1 X 11 101 101 2 4 16 C to Au A B B 1 10 100 011 B to Ax Al HL HL 1 C HL 1 X X I X 11 101 101 2 5 21 C to An A B B 1 10 110 011 If B O B to Ax Ala HL HL 1 2 4 16 Re peat until B O If BoO CD ...

Page 109: ...that the two s complement num ber in the accumulator is in error since it has exceeded the maximum possible 127 or is less than the mini mum possible 128 number than can be represented in two s complement notation For example consider adding 120 011 I 1000 105 0110 1001 C 0 1110 0001 31 wrong Overflow has occurred Here the result is incorrect Overflow has occurred and yet there is no carry to indi...

Page 110: ...e operation indicated a match between the source and the accumulator data Also the parity flag is set if the byte counter register pair BC is not equal to zero This same use of the parity flag is made with the block move instructions Another special case is during block input or output instructions here the Z flag is used to indicate the state of register B which is used as a byte counter Notice t...

Page 111: ...of the operation is zero S Sign flag S I if the MSB of the result is one P V Parity or overflow flag Parity P and overflow V share the same flag Logical operations affect this flag with the parity of the result while arithmetic operations affect this flag with the overflow of the result If P V holds parity P V 1 if the result of the operation is even P V 0 if result is odd If P V holds overflow P ...

Page 112: ...ained A reset to the CPU will force both IFF1 and IFF2 to the reset state so that interrupts are disabled They can then be enabled by an EI instruction at any time by the programmer When an EI instruction is executed any pending inter rupt request will not be accepted until after the instruction following EI has been executed This single instruction delay is necessary for cases when the following ...

Page 113: ...will execute it Thus the interrupting device provides the next instruction to be executed instead of the memory Often this will be a restart instruction since the interrupting device only need supply a single byte instruction Alternatively any other instruction such as a 3 byte call to any location in memory could be executed The number of clock cycles necessary to execute this instruction is 2 mo...

Page 114: ...arting address and the addresses must always start in even locations Interrupt Service Routine Starting Address Table low order high order desired starting address pointed to by IREG 7 BITS FROM CONTENTS PERIPHERAL 0 The first byte in the table is the least significant low order portion of the address The programmer must obviously fill this table in with the desired addresses before any interrupts...

Page 115: ... interrupt controlled handshake Daisy chain priority interrupt logic included to provide for automatic interrupt vectoring without external logic Eight outputs are capable of driving Darlington transistors All inputs and outputs fully TTL compatible Single 5 volt supply and single phase clock are required One of the unique features of the Z 80A PIO that separates it from other interface controller...

Page 116: ...face directly to peripheral devices DATA US CPU INTERFACE 6 f Dt PIO CONTROL LINES 3 INTERRUPT CONTROL LINES FIGURE 2 0 1 PIO BLOCK DIAGRAM Kf 8 f 1 DATA OR CONTROL 1 1 HANDSHAKE PERIPHERAL INTERFACE The Port I 0 logic is composed of 6 registers with handshake control logic as shown in Figure 1 0 2 The registers include an 8 bit data input register an 8 bit data output register a 2 bit mode contro...

Page 117: ... device is determined by its physical location in a daisy chain configuration Two lines are provided in each PIO to form this daisy chain The device closest to the CPU has the highest priority Within a PIO Port A inter rupts have higher priority than those of Port B In the byte input byte output or bidirectional modes an interrupt can be generated whenever a new byte transfer is requested by the p...

Page 118: ...the standard Z SOA system clock to synchronize certain signals internally This is a single phase clock M1 Machine Cycle One Signal from CPU input active low IORQ RD This signal from the CPU is used as a sync pulse to control several internal PIO operations When MI is active and the RD signal is active the Z 80A CPU is fetching an instruction from memory Conversely when M1 is active and IORQ is act...

Page 119: ...rectional data bus The positive edge of the strobe acknowledges the receipt of the data 4 Control mode The strobe is inhibited internally A RDY Register A Ready output active high The meaning of this signal depends on the mode of operation selected for Port A as follows 1 Output mode This signal goes active to indicate that the Port A output register has been loaded and the peripheral data bus is ...

Page 120: ... 2 7 A7 PORT B A SEL 6 18 A ROY CONTROL DATA SEL 5 Z80A PIO 16 A STB PIO CHIP ENABLE CONTROL Ml 4 27 37 28 8 o 81 IORQ 36 29 8 2 RD 35 30 8 3 31 8 4 5V GND 26 32 33 II 34 8 5 PORT B 1 0 8 6 8 7 I 25 21 B RDY INT INTERRUPT CONTROL INT ENABLE IN INT ENABLE OUT 17 23 24 22 B STB FIGURE 3 0 1 PIO PIN CONFIGURATION ...

Page 121: ... PIO has entered the internal reset state it is held there until the PIO receives a control word from the CPU 4 2 LOADING THE INTERRUPT VECTOR The PIO has been designed to operate with the Z 80A CPU using the mode 2 interrupt response This mode re quires that an interrupt vector be supplied by the interrupting device This vector is used by the CPU to form the address for the interrupt service rout...

Page 122: ...been enabled and causes the Ready line to go inactive This very simple handshake is similar to that used in many peripheral devices Selecting Mode 1 puts the port into the input mode To start handshake operation the CPU merely performs an input read operation from the port This activates the Ready line to the peripheral to signify that data should be loaded into the empty input register The periph...

Page 123: ...t will then be enabled onto the CPU interrupt request line Bits D6 D5 and D4 are used only with Mode 3 operation How ever setting bit D4 of the interrupt control word during any mode of operation will cause any pending interrupt to be reset These three bits are used to allow for interrupt operation in Mode 3 when any group of the I 0 lines go to certain defined states Bit D6 AND OR defines the log...

Page 124: ...omatically generates an INT request if the inter rupt enable flip flop has been set and this device is the highest priority device requesting an interrupt If the PIO is not in a reset state the output register may be loaded before mode 0 is selected This allows the port output lines to become active in a user defined state PORT OUTPUT f f 5 BITS FIGURE 5 0 1 READY MODE 0 OUTPUT TIMING INT WR RD CE...

Page 125: ...OY WR RD CE C D IORQ FIGURE 5 0 3 PORT A MODE 2 BIDIRECTIONAL TIMING The peripheral must not gate data onto a port data bus while A STB is active Bus contention is avoided if the peri pheral uses B STB to gate input data onto the bus The PIO uses the B STB low level to latch this data The PIO has been designed with a zero hold time requirement for the data when latching in this mode so that this s...

Page 126: ...Ml is active The highest priority device places the contents of its interrupt vector register onto the Z80 data bus during interrupt acknowledge Figure 6 0 1 illustrates the timing associated with interrupt requests During Ml time no new interrupt requests can be generated This gives time for the Int Enable signals to ripple through up to four PIO circuits The PIO with lEI high and lEO low during ...

Page 127: ...PT OCCURS_ UNDER SERVICE LO lEI lEO 2 PORT 2A REQUESTS AN INTERRUPT AND IS ACKNOWLEDGED UNDER SERVICE lEO 3 PORT 18 INTERRUPTS SUSPENDS SERVICING OF PORT 2A SERVICE COMPLETE SERVICE RESUMED HI HI lEO 4 PORT 18 SERVICE ROUTINE COMPLETE RETI ISSUED PORT 2A SERVICE RESUMED lEO 5 SECOND RETI INSTRUCTION ISSUED ON COMPLETION OF PORT 2A SERVICE ROUTINE FIGURE 6 0 3 DAISY CHAIN INTERRUPT SERVICING ...

Page 128: ...CPU is assured to be from the highest priority device which requested an interrupt If more than four PIO devices must be accommodated a look ahead structure may be used as shown in Figure 7 0 1 With this technique more than thirty PIO s may be chained together using standard TTL logic DATA BU S FIGURE 7 0 1 A METHOD OF EXTENDING THE INTERRUPT PRIORITY DAISY CHAIN 7 2 1 0 DEVICE INTERFACE In this e...

Page 129: ... Manual for details on the operation of the interrupt 0 Interrupts are then enabled by the rising edge of the first M1 after the interrupt mode word is set unless that M1 defines an interrupt acknowledge cycle If a mask follows the interrupt mode word interrupts are enabled by the rising edge of the first M1 following the setting of the mask Data can now be transferred between the peripheral and t...

Page 130: ... System Alarm PORT A BUS A7 ZSOA PIO As v A5 v A4 A3 v A2 A v Ao v B A C D CE I t FIGURE 7 0 3 CONTROL MODE APPLICATION SPE C TEST TURN ON PWR PWR FAIL AL M HALT INDUSTRIAL PROCESSING TEMP ALM SYSTEM HTRS ON PRESS SYS PRESS ALM The PIO may be used as follows First Port A is set for Mode 3 operation by writing the following control word to Port A X X Whenever Mode 3 is selected the next control wor...

Page 131: ...upt request would also occur if bit A7 Special Test of the output register was set Assume that the following port assignments are to be used EOH Port A Data ElH Port B Data E2H Port A Control E3H Port B Control All port numbers are in hexadecimal notation This particular assignment of port numbers is convenient since A0 of the address bus can be used as the Port B A Select and A1 of the address bu...

Page 132: ...Sets bit to Output 8 3 SET INTERRUPT CONTROL Int AND High Mask 0 I Enable OR Low Follows Used in Mode 3 only 1 I If the mask follows bit is high the next control word written to the port must be the mask MBo MB 0 Monitor bit MB I Mask bit from being monitored 125 Also the interrupt enable flip flop of a port may be set or reset without modifying the rest of the interrupt control word by using the ...

Page 133: ...temp 15 to 60 C 80 characters x 25 lines n H 1 2 software change over Humidity Lower than 80 Graphic display option Weight II Approx 16 kg 320 x 200 dots Two graphic areas Dimensions n M i Width 450mm Cassette Standard audio cassette tape Depth 520mm Data transfer speed 1800 bits sec Height 270mm Data transfer system SHARP PWM Automatic or manual control i ii Sound output Max 400 mW 440 Hz 2 CPU B...

Page 134: ...ical 8 12 max Pincushion dist 1 2 max Barrel dist 1 2 max Trapezoidal dist 1 2 max Parallelogram dist 1o 2 5 max Zero beam ll OkV lO OkV min 12 0kV max 12Hz 6Hz limit Audio 440Hz OdB frequency 1OdB 4dB at 1OOHz charaCteristic 12dB 4dB at 1OkHz 5 CASSETTE TAPE DECK SECTION SPECIFICATIONS System Power source Semiconduc tors Tape Tape speed Track PWM recording 5V 5 12V 5 stabilizing 9 5V l6 5V non st...

Page 135: ...ly pull the power plug and contact your dealer Shock If the unit is subjected to shock the sensitive electronic parts may be damaged Trouble If any trouble occurs stop operating the unit immediately and contact your dealer Long periods of disuse When the unit is not operated for a long time be sure to pull the power plug from the AC outlet Connection of peripheral devices When connecting periphera...

Page 136: ...intenance Dirty cassette deck recording and reproducing heads may result in incorrect data recording the reproduction Be sure to clean the heads every month Commercially available cleaning tape is convenient Discoloration of CRT screen If a certain spot of the CRT screen is lit an external period of time the spot may become discolored If it is neces sary for certain spot to be lit for an extended ...

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