15
RESET
signal
V
S1
(4.5V)
V
CPU
V
HYS1
(15mV)
T
PO
T
PO
T
PO
POWER OFF
DETECTION
signal
V
S2
(4.15V)
V
CC
V
HYS2
(200mV)
Fig.8
Fig.9
When the power is turned on, V
LCD
, V
CC
and V
CPU
rise. If V
CPU
exceeds V
S1
+V
HYS1
, the RESET
signal is shifted to “High” level at the timing shown in Fig. 10. The reset operation of IC400 is
canceled and executes the program.
When the power is turned off, the power OFF detection signal is shifted to “Low” when V
CC
and
V
LCD
drops sharply below V
S2
.
On the other hand, Vcpu is backed up by C425 (220mF) so that it can maintain 4.5V for the time
of TW after the trailing edge of the power OFF detection signal. See Fig. 11. (TW is the time
for IC400 to retreat the data to EEPROM.) If V
CPU
drops below V
S1
, the RESET signal level is
shifted to “Low”, and IC400 starts resetting.
Summary of Contents for QD-101MM
Page 39: ...38 6 CIRCUIT DIAGRAM PWB Fig 27 CIRCUIT DIAGRAM MAIN CIRCUIT No 1 ...
Page 40: ...39 Fig 27 CIRCUIT DIAGRAM MAIN CIRCUIT No 1 ...
Page 41: ...40 Fig 28 CIRCUIT DIAGRAM MAIN CIRCUIT No 2 ...
Page 42: ...41 Fig 28 CIRCUIT DIAGRAM MAIN CIRCUIT No 2 ...
Page 43: ...42 Fig 29 CIRCUIT DIAGRAM MAIN CIRCUIT No 3 ...
Page 44: ...43 Fig 29 CIRCUIT DIAGRAM MAIN CIRCUIT No 3 ...
Page 45: ...44 Fig 30 CIRCUIT DIAGRAM MAIN CIRCUIT No 4 ...
Page 46: ...45 Fig 30 CIRCUIT DIAGRAM MAIN CIRCUIT No 4 ...
Page 47: ...46 Fig 31 CIRCUIT DIAGRAM POWER CIRCUIT ...
Page 48: ...47 Fig 31 CIRCUIT DIAGRAM POWER CIRCUIT ...
Page 49: ...48 Fig 32 CIRCUIT DIAGRAM VIDEO CIRCUIT ...
Page 50: ...49 Fig 32 CIRCUIT DIAGRAM VIDEO CIRCUIT ...
Page 51: ...50 Fig 33 CIRCUIT DIAGRAM AUDIO CIRCUIT ...
Page 52: ...51 Fig 33 CIRCUIT DIAGRAM AUDIO CIRCUIT ...
Page 53: ...52 Fig 34 PWB PATTERN MAIN PWB FRONT SIDE ...
Page 54: ...53 Fig 34 PWB PATTERN MAIN PWB REAR SIDE ...
Page 66: ...PRINTED IN GERMANY ...