UP-3301US
CIRCUIT DESCRIPTION
– 44 –
39
CTS2Z
/CTS3
IS
RS-232 clear to send signal
40
RCVDT2
RCVDT3
IS
RS-232 reception to send
signal
41
/CI2
VCC
IS
+5V
42
/CS2
/CS3
O
RS-232 chip select signal
43
/CD3
/SINT
IS
RS-232: /CD, IN-LINE : /P1
44
BRK3
GND
IS
GND
45
TRNEMP3
GND
IS
GND
46
RCVRDY3
GND
IS
GND
47
TRNRDY3
GND
IS
GND
48
/CTS3
GND
IS
GND
49
RCVDT3
GND
IS
GND
50
/CI3
GND
IS
GND
51
/CS3
/SRCS
O
RS-232/INLINE chip select
signal
52
D0
D0
IO
Data bus (CPU)
53
D1
D1
IO
Data bus (CPU)
54
D2
D2
IO
Data bus (CPU)
55
D3
D3
IO
Data bus (CPU)
56
GND
GND
GND
57
D4
D4
IO
Data bus (CPU)
58
D5
D5
IO
Data bus (CPU)
59
D6
D6
IO
Data bus (CPU)
60
D7
D7
IO
Data bus (CPU)
61
GND
GND
GND
62
VCC
VCC
+5V
63
X1
NC
O OSI14 NC
64
X2
#
I OSI14 System clock
65
XOUT
CLK_USART
O
Clock (USART)
66
TRCK
NC
O
NC
67
AB0
AH0
O
Address bus for USART
68
AB1
AH1
O
Address bus for USART
69
US1CH
GND
IS
GND
70
PX
NC
O
NC
71
/POF
/POFF
IS
POFF signal
72
/RSRQ
/IRQ1
3S
RS232 INTERRUPT
73
/TRV
GND
IS
GND
74
RXDATA0
NC
O
NC
75
TXE
/SRESET
O
INLINE TRNS ENABLE
76
/TRRQ
/TRQ2
3S
INLINE INTERRUPT
77
/TRQ1
/TRQ1
ON6
TIMER INTERRUPT
(RS232)
78
/TRQ2
NC
ON6
TIMER INTERRUPT
(INLINE)
79
A0
A0
I
Address bus for CPU
80
A1
A1
I
Address bus for CPU
81
A2
A2
I
Address bus for CPU
82
A3
A3
I
Address bus for CPU
83
A4
A4
I
Address bus for CPU
84
A5
A5
I
Address bus for CPU
85
/OPTCS
/OPTCS
I
Option chip select (from
MPCA)
86
/RD
/RDO
I
Read signal (from CPU)
87
/WR
/WRO
I
Write signal (from CPU)
88
/RES
/RES
IS
Reset signal (from CPU)
Pin
NO.
Name
UP-3301
I/O
Description
89
DB0
DB0
IO
DATA BUS (USART)
90
DB1
DB1
IO
DATA BUS (USART)
91
DB2
DB2
IO
DATA BUS (USART)
92
DB3
DB3
IO
DATA BUS (USART)
93
GND
GND
GND
94
DB4
DB4
IO
DATA BUS (USART)
95
DB5
DB5
IO
DATA BUS (USART)
96
DB6
DB6
IO
DATA BUS (USART)
97
DB7
DB7
IO
DATA BUS (USART)
98
/R
/RDH
O
Read signal (to USART)
99
/W
/WRH
O
Write signal (to USART)
100
VCC
VCC
+5V
101
GND
GND
GND
102
RES
RES USART
O
Reset signal (to USART)
103
TRNCLK
GND
I
GND
104
RCVCLK
GND
I
GND
105
DBTST
/SRCS
ID
RS-232/INLINE USART chip
select
106
UTST
VCC
ID
+5V
107
/CSA
/CS1
IS
USART_A chip select
108
TRNDTA
TXD1
O
RS-232 transmission data
signal
109
/DTRA
/DTR1
O
RS-232 data terminal ready
signal
110
/RTSA
NC
O
NC
111
RCVDTA
RCVDT1
IS
RS-232 reception data sig-
nal
112
/CTSA
GND
IS
GND
113
/DSRA
/DSR1
IS
RS-232 data set ready sig-
nal
114 TRNRDYA
TRNRDY1
O
RS-232 data transmission
enable signal
115 RCVRDYA
RCVRDY1
O
RS-232 data reception
enable signal
116 TRNEMPA
TRNEMP1
O
RS-232 transmission buffer
empty signal
117
SYCBKA
BRK1
IO
Break code detection signal
118
GND
GND GND
119
/CSB
/CS2
IS
USART_B chip select
120
TRNDTB
TXD2
O
RS-232 transmission data
signal
121
/DTRB
/DTR2
O
RS-232 data terminal ready
signal
122
/RTSB
NC
O
NC
123
RCVDTB
RCVDT2
IS
RS-232 reception data sig-
nal
124
/CTSB
GND
IS
GND
125
/DSRB
/DSR2
IS
RS-232 data set ready sig-
nal
126 TRNRDYB
TRNRDY2
O
RS-232 data transmission
enable signal
127 RCVRDYB
RCVRDY2
O
RS-232 data reception
enable signal
128 TRNEMPB
TRNEMP2
O
RS-232 transmission buffer
empty signal
129
SYCBKB
BRK2
IO
Break code detection signal
130
GND
GND
GND
131
/CSC
/CS3
IS
USART_C chip select
Pin
NO.
Name
UP-3301
I/O
Description
Summary of Contents for UP-3301
Page 91: ...UP 3301US PWB LAYOUT 89 CHAPTER 9 PWB LAYOUT 1 MAIN PWB A side ...
Page 92: ...UP 3301US PWB LAYOUT 90 B side 8 CUSTOMER DISPLAY PWB ...
Page 93: ...UP 3301US PWB LAYOUT 91 2 IR PWB 3 LCD PWB A Side B Side 4 INVERTER PWB A Side B Side ...
Page 94: ...UP 3301US PWB LAYOUT 92 5 MOTHER PWB 6 N F PWB 7 TOUCH PANEL PWB ...
Page 95: ...UP 3301US PWB LAYOUT 93 ...
Page 111: ......