Sharp UP-5700, Service Manual

Page 1: ... sure to replace these parts with specified ones for maintaining the safety and performance of the set WIRING DIAGRAM CHAPTER 1 SPECIFICATIONS 1 1 CHAPTER 2 OPTIONS 2 1 CHAPTER 3 SERVICE PRECAUTION 3 1 CHAPTER 4 DIAGNOSTICS SPECIFICATIONS 4 1 CHAPTER 5 CIRCUIT DESCRIPTION 5 1 CHAPTER 6 POWER SUPPLY UNIT 6 1 CHAPTER 7 BIOS SET UP UTILITY 7 1 CHAPTER 8 ABOUT UTILITY SOFTWARE AND OTHERS 8 1 CHAPTER 9...

Page 2: ... the end of their useful life when taken out of service within the United States The RBRCTM program provides a convenient alternative to placing spent nickel cadmium battery packs into the trash or municipal waste stream which is illegal in some areas SHARP s payments to RBRCTM makes it easy for you to drop off the spent battery pack at local retailers of replacement nickel cadmium batteries or at...

Page 3: ...eo RAM 1 Mbytes EDO type BIOS ROM 512 Kbytes Flash ROM OS MS DOS ROM 4 Mbytes Mask ROM ROM disk memory for stored Application software Standard 2 Mbytes Flash ROM Max 6 Mbytes adding UP F04RB RAM disk memory for POS data Standard 1 Mbytes Max 3 Mbytes adding UP P02MB Key controller M38802 Super I O M5113 3 4 Serial port D SUB 9 pin connector COM1 and COM2 are equipped In order to supply 5V power C...

Page 4: ...utdown switch needs to be set to this position when the UP 5700 is operated Operating method The shutdown switch is a push switch If it is push ON UP 5700 performs to stop supplying the power when the power switch is set into stand by mode NOTE The shutdown operation will be ignore when te power switch is set into power on position 3 7 System switch The system switch is used to preset for system c...

Page 5: ... trol the power supply to hold even if the power switch is set into this position power supplying will be kept until an software program allows power supply no to hold Operating method The power switch is a seesaw switch and it can be tipped toward the ON or OFF 4 Software 4 1 Software Structure The basic system software is mainly consisted of the following 3 modules 1 MS DOS Version 6 22 The oper...

Page 6: ...ration utility program MS DOS These software are provided with FD from SHARP Please copy contents of FD provided from department to development PC Install to UP 5700 by using APL Install Program from PC 4 3 Memory map 0000000h 0800000h 1000000h 1800000h 2800000h STD 8MB 8MB 16MB 8MB 24MB 32MB 40MB 00000h 9F4000h A0000h C0000h CB000h E8000h 100000h MS DOS 25K Sharp Driver 32K Free Conventional 580K...

Page 7: ...232 Communication Connection Remote Printer Option ER 01PU supplied on site TM T80 85 295 ER FBT40 Hand Scanner Option ER A6HS1 max 2 RS 232 max 6 2 Options No NAME MODEL NAME DESCRIPTION 1 Expansion RAM disk board UP P02MB 2 Mbytes RAM board 2 Expansion ROM disk board UP F04RB 4 Mbytes ROM board 3 Customer display ER A8DP 1 line 7 segments display 4 Customer pole display UP P20DP 2 line 20 digits...

Page 8: ...connector 8 BIOS MASTER ROM P EP ROM for overwriting BIOS 9 TOUCH PEN AG For TOUCH PANEL POSITION ADJUSTING UTILITY PROGRAM 1 1 Always use this pen for the TOUCH PANEL POSITION ADJUSTING UTILITY PROGRAM This pen is for K PDA ZR xxxx series If you use a ball point pen or other pens whose point is hard the surface of TOUCH PANEL may be damaged 4 1 Service tool kit DKIT 8656BHZZ 1 ISA checker Used to...

Page 9: ... PWB relay board UP 5700 Not used External view Plan view UP 5700 ISA bus connector ER A8RS or ER 01IN PC ISA checker ISA bus connector Used to check the ER A8RS or ER 01IN PC solder side Connected to the ISA bus connector of ISA checker ISA bus connector Used to check the ER A8RS or ER 01IN PC parts side ER A8RS or ER 01IN PC solder side ISA relay board ER A8RS or ER 01IN PC parts side ISA PWB IS...

Page 10: ...xecuting diagnostics Connection diagram 4 5 RS232 modular jack loop back connector UKOG 6729BHZZ Connected to the RS232 connector RJ45 COM5 COM6 of the UP 5700 and ER A8RS and used to check loop signals when exe cuting diagnostics Connection diagram 150 8 Signal name Pin No 1 STROBE 2 DB0 3 DB1 4 DB2 5 DB3 6 DB4 7 DB5 8 DB6 9 DB7 10 ACK 11 BUSY 12 PE 13 SLCT 14 AUTOFD 15 ERROR 16 INIT 17 SLCTIN 18...

Page 11: ...is a tool to write a BIOS ROM program in the F ROM on the UP 5700 s main board Use this PWB in the following cases The F ROM on the UP 5700 s main board is changed due to some defect and a BIOS ROM program is written in the F ROM The BIOS ROM program in the F ROM is overwritten due to the version up of BIOS ROM program etc Connected to the Option ROM RAM disk connector CN19 of the Main PWB Externa...

Page 12: ...ction diagram Writing BIOS ROM Program 1 Install the EP ROM master ROM VHI27040RBH1A containing a BIOS program on the BIOS loading board CKOG 6727RCZZ LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 1 3 SW1 BIOS MASTER ROM 2 6 ...

Page 13: ...status of LED on the special service PWB when a BIOS ROM program is being written see the following table Writing is complete automatic completion when the green LED LED9 on the BIOS loading board lights up 6 After writing is complete turn off the power switch on the right side to remove the BIOS loading board and turn on the power switch on the left side again to check whether the BIOS program st...

Page 14: ...rifying Bank0 D0000 h 64KB Verifying Bank0 E0000 h 64KB Verifying Bank0 F0000 h 64KB Verifying Bank1 C0000 h 64KB Verifying Bank1 D0000 h 64KB Verifying Bank1 E0000 h 64KB Verifying Bank1 F0000 h 64KB Setting protection the F ROM END of complete COPY FUNCTION Erase ERROR in F ROM LED1 RED LED2 RED LED3 RED LED4 RED LED5 RED LED6 RED LED7 RED LED8 RED LED9 GREEN FUNCTION Device not ready VPP error ...

Page 15: ...connected Be careful not to give a stress to the heat seal section when installing The touch panel is provided with an air groove to make the exter nal and the internal air pressure equal to each other If water or oil is put around the air groove it may penetrate inside Be careful to keep the air groove away from water and oil Input is performed with fingers Do not use a hard thing for input ting ...

Page 16: ...tom of the connec tor s insulator 3 Close the slider to lock position Insert the FFC and then push the slider downward 4 To pull out the FFC unlock the slider to pull it out in the same procedures as 1 6 AT Keyboard usable for UP 5700 Do not use the following keyboards because they do not work when connected to the UP 5700 The UP 5700 can be externally connected to a keyboard The UP 5700 s key BIO...

Page 17: ...Read Test 16 6 HD Dump Test 17 7 Error lnformation Display 17 8 Contoroller check Test 18 WRITE MODE TEST 18 9 Seek Write Read Verify Test 18 10 Target Sector Write Read Verify Test 19 11 HDPatch Test Utility 19 12 Error Logging Area Clear 19 13 Error table display 19 14 Other Supplemental Items 19 15 Error Content 20 16 Error Information Storing Area Description 20 3 18 FAN LCD ON OFF Diagnostics...

Page 18: ...checked in the unit of 64KB The check procedures are as follows i Test data 5555H is written to all the test areas ii Test data and read data are compared for each word If it is O K test data AAAAH is written to the test area iii Test data and read data are compared for each word If it is O K test data 5555H is written to the test area iv Test data 0000H is written to all the test areas v Test dat...

Page 19: ...terminated ii Test data 55AAH is written to BANK 040H 0D4000H iii BANK 040H 0D4000H is read and compared with 55AAH If both data are correct the following test is executed If not Extended RAM Disk size 0KB is displayed and the test is terminated iv The test area data is saved to the main memory v Test data 5555H is written to the test area vi Test data and read data are compared If is OK test data...

Page 20: ...alue is not read the following display is made Esc key When YES is selected Move cursor to select YES and the message in will be displayed If the verify check is made the test area is first erased Increment data for each byte is written to all the test areas Example 0001h 0203h 0405h 0E0Fh FEFFh The two left digits are the lower address and the two right address are the upper address Read verify c...

Page 21: ...ly when an error occurs When no error occurs they are not displayed Terminating method After the test result is displayed press Esc key to terminate 3 6 Touch Panel Diagnostics The touch panel and its controller are checked Communication with the controller is performed by 8250 built in the gate array PSC2 The controller diag check the touch keypad test and the linearity test are performed The ini...

Page 22: ...A8RS parallel interface option are tested Here parallel interface on the main body is mentioned as PARAL LEL1 and parallel interface on ER A8RS as PARALLEL 2 3 The following menu is displayed The highlighted cursor is moved by the cursor keys UP and DOWN of the AT keyboard Move the cursor to the desired item and press Enter key to execute the selected diagnostics program When the selected diagnost...

Page 23: ...11 12 13 14 ERROR 15 INIT SLCTIN 16 17 18 2 Loop cable UKOG 6717RCZZ wiring diagram GND J9 L H 5 7 J10 I O 1 0 J3 J8 J4 J5 J6 J7 1 2 J18 J11 J12 J13 J14 J15 J16 J17 UP 5700 PARALLEL1 OUTPUT MODE A8RS PARALLEL3 INPUT MODE Opposite ER A8RS setting Jumper pin setting diagram PARALLEL1 Loop Check ACK Signal PASS or ERROR INTERRUPT IRQ X or ERROR BUSY Signal PASS or ERROR PE Signal PASS or ERROR SLCT S...

Page 24: ... terminate 5 PARALLEL2 Print Check Check content The print check is performed for PARALLEL2 at I O address 278H 27Fh on the ER A8RS In the print check set the short pin of the ER A8RS to be tested as shown in Fig 3 9 and connect D Sub 25 pin connector to the printer to allow to print for test Fig 3 9 Jumper pin setting The test procedures are as follows i Data of 55H is written to I O address 278H...

Page 25: ... keys UP and DOWN of the AT keyboard Move the cursor to the desired item and press Enter key to execute the selected diagnostics program When the selected diagnostics program is completed the display returns to the menu screen Pressing Esc key returns to the service man diagnostics menu 1 COM1 Check Content The loop back check is performed for UART at I O address 3F8H 3FFH The test procedures are ...

Page 26: ...OM5 Check Check content The loop back check is performed for UART at I O address PSC2 base address 410H 417H The following points are different from COM1 Check Content RTS CTS is not checked DTR RI is not checked Display RTS CTS is not displayed DTR RI is not displayed COM5 is checked as well as COM1 except the above 2 points 6 COM6 Check Check content The loop back check is performed for UART at ...

Page 27: ...ollowing test pattern is displayed ii The test pattern of all digits ON is displayed Display Terminating method Pressing Esc key clears the rear display and terminates the test HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH...

Page 28: ...The interruption of CTC CH2 or CH3 timer interruption is not made b1 ROM SUM CHECK ERROR b0 RAM ERROR iii Diag 1 command is executed and the error status is dis played The error status is as shown in the figure below b7 An error is generated Always 1 in case of error print b6 An unexpected interruption is made b5 Data transmitted by DMA is different from date received b4 The number of data receive...

Page 29: ... in the menu The Terminal number is read from the DIP SW1 ER 01 IN and the following procedures are performed The fol lowing display will be shown If the Terminal No is setting for 255 FFH the display below will be shown and the following procedures are not per formed Change the terminal number and press the ESC key then the display will return to the service man diagnostics menu screen Retry the ...

Page 30: ...ication among many poles and time out of data transmission wait time is generated 09 Reception size over when receiving The reception buffer size is insufficient 0A Hard error Interface abnormality No SRN interface or SRN controller abnormality Terminating method Press Esc key to terminate the check When terminating the check reset the software of SRN inside the PSC 3 13 Magnetic Card Reader Diagn...

Page 31: ...en Drawer 1 and Drawer 2 are connected CLOSE is dis played only when both the drawers are closed Display Terminating method Press Esc key to terminate the test 2 Drawer 2 Check Check content Drawer 2 solenoid is turned on and the drawer open sensor value is sensed at every 100ms and the state is displayed When Drawer 1 and Drawer 2 are connected CLOSE is dis played only when both the drawers are c...

Page 32: ...t or not Check content In the cylinder range set above sequential seek is executed for every 1 track When seek test in the set range is completed in the direction of 0 inmost cylinder it is counted as 1 pass In case of an error during the above test retry is repeated up to the set number of retry Every time when an error occurs by executing retry up to the retry number error logging is performed L...

Page 33: ...y one track is executed in the cylinder range and the sector range set above in the direction of 0 inmost cylinder When read test is completed in the set range it is counted as 1 pass Before seeking however seek is made the previous cylinder and the following cylinder Head movement When track N is read the head moves as follows At and read is executed In case of an error during the above test retr...

Page 34: ...tor No 1 final sector A certain sector No to be displayed is set Check content The sector set in the above is displayed on the screen in the unit of 256byte Hex data and ASCII characters are displayed By key operation the following 256 byte data or previous 256byte data can be displayed Display The physical address is set at position of On the above screen the thick value is set On the above scree...

Page 35: ...t Test conditions setting Similar to the above 4 Cylinder range setting is 000 inmost cylinder 2 Check content For all the cylinder range and the sector range set in the above the worst pattern data is written sequentially for every one track Then read verify check is made for every one track The number of read verify check is one Test for 1 pass Write is made in the direction of 0 inmost cylinder...

Page 36: ...range 000 XXX XXX is inmost cylinder 2 Test mode is displayed When data writing WRITE is displayed in When data reading READ is displayed Terminating method Same as 5 11 HD Patch Test Utility Test conditions setting Similar to the previous 6 The cylinder range setting is 000 Final cylinder 2 Check content The sector set in the above is displayed on the screen in the unit of 256byte Hex data and AS...

Page 37: ...g format from the head of each sector Error information format for every sector 1 46 11 507byte is used in one sector 3 18 Fan LCD ON OFF Diagnostics 1 Fan LCD ON OFF Check Check content The CPU the fan the exhaust fan and the LCD are turned ON OFF When this menu is selected the following display is shown When any key is pressed 1 is written to bit 4 of PSC2 general use I O port HIOP At that time ...

Page 38: ...KDC VII I F ER A8DP I F Mode Switch Sense 16bits Not used Clerk Switch Sense 16bits UP 5700 supports 76 its clerks MCR I F 2track Drawer I F 4drawers UP 700 supports 2drawers 1 7 Memory L2 cache None System Memory DRAM Standard 1M 16b EDO Asym 60ns Vcc 3 3V 4chip 8MB Option 144pin S O DIMM socket 1 8MB 16MB 32MB 64MB Fu ture BIOS ROM 512K 8b 512KB Flash ROM Vcc 5 0V DOS ROM 2M 16b 4MB Mask ROM Vcc...

Page 39: ... ER A8DP Customer Display Option for ECR ER A8RS RS 232C Centronics Interface Board 2 Block Diagram CPU PCB Main PCB Key I F PCB CCFT Inveter LCD Analog Touch Panel POS Keyboard TPC NO10 0559 V021 Clerk SW Mode SW System SW COM3 5 COM4 6 UP P20DP ER A8DP Drawer MCR PSC2 ISA Bus Std PS RAM Disk 1MB 0pt PS RAM Disk 2MB Std F ROM Disk 2MB 0pt F ROM Disk 4MB DOS ROM 4MB BIOS ROM 512kB ISA slot ER A8RS...

Page 40: ...0 C9FFF CC000 2800000 E8000 EC000 47FFFFF F0000 FFFFF Not used System BIOS 64KB RAM Disk 16KB ROM Disk 16KB M ROM Bank0 255 F ROM Bank512 895 PS RAM Bank0 191 UMB 112KB VGA BIOS 40KB VGA RAM 128KB EDO DRAM Option 8Byte SOD 32MB EDO DRAM Option 8Byte SOD 16MB EDO DRAM Option 8Byte SOD 8MB EDO DRAM Standard 8MB 5 3 ...

Page 41: ... 3DF EGA VGA control 3E0 3E4 PCIC PCMCIA controllers 3E5 BIOS ROM Write Control 3E6 3E7 PCIC PCMCIA controllers 3E8 3EF COM3 control 3F0 3F7 FD HD control 3F8 3FF COM1 control 400 40A 40B 4D6 EISA DMA Extended Mode control 4D7 7EF 7F0 7F1 PSC Special System Register 7F2 7FF Address Legacy ISA I O 800 A78 A79 PnP ISA Auto Configuration Port A7A CF7 CF8 CFF PCI Configuration D00 FFF Address POS I O ...

Page 42: ...5 IRQx15 NU or Clerk Switch S1 IRQ10 1 ON Connect IRQ10 to the ISA Slot 3 OFF Connect IRQ10 to GND not to the ISA Slot S2 IRQ11 1 ON Connect IRQ11 to the ISA Slot 3 OFF Connect IRQ11 to GND not to the ISA Slot 5V 10K 0 2 7K 2 7K 0 5V 10K FireStar IRQ9 5V 10K 0 2 7K 5V 10K 5V 1K IRQ10 IRQ11 SICF IRQ9 IRQ3 IRQ4 IRQ5 5V 10K 1K 5V 10K 5V 10K 0 5V 10K 5V 22K 5V 10K Penrium IRQ15 IRQ3 IRQ4 IRQ10 IRQ11 I...

Page 43: ... 66MHz 1 2 1 0 120MHz 60MHz 1 2 1 0 UP 5700 Setting 100MHz 66MHz 2 3 1 1 90MHz 60MHz 2 3 1 1 75MHz 50MHz 2 3 1 1 Setting 1 10kohm Pull up Vcc3 0 0ohm Grounding Micro Clock MK1438 04R Clock Generator CPU Clock Decording Table TENTATIVE CPU Clock PCI Clock FS1 FS0 Selection pins 10 12 13 pin 9 pin 1 pin 11 60MHz 33 33MHz 0 0 50MHz 33 33MHz 0 1 75MHz 33 33MHz NC 0 55MHz 33 33MHz NC 1 66 66MHz 33 33MH...

Page 44: ...N NC STPCLK NC VSS VCC3 VCC2 U VSS T CACHE M O INV VCC3 VCC3 VSS VSS VCC3 VCC2 S VSS R BP2 PMIBP1 BP3 NC NC NC VSS VCC3 VCC2 Q VSS P PMOBP0 IERR FBRR TRST TMS NC VSS VCC3 VCC2 N VSS M D63 D62 DP7 TDO TCK TDI VSS VCC3 VCC2 L VSS K D61 D59 D60 VCC3 D0 NC VSS VCC3 VCC2 J VSS H D57 D56 D58 NC NC D2 VSS VCC3 VCC2 G DP6 F D55 D51 D53 DP5 D3 D5 D1 D4 VCC3 D54 E D50 D D52 D48 D49 D44 D46 D40 D42 D39 D37 D...

Page 45: ...0 bits in the Debug Mode Control Register determine if the pins are configured as breakpoint or performance monitoring pins The pins come out of RESET configured for performance monitoring BRDY I The burst ready input indicates that the external system has presented valid data on the data pins in response to a read or that the external system has accepted the processor data in response to a write ...

Page 46: ...erted When the CR0 NE bit is 0 IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating point instruction is one of FINIT FCLEX FSTENV FSAVE FSTSW FSTCW FENI FDISI or FSETPM the processor will execute the instruction in spite of the pending exception When the CR0 NE bit is 0 IGNNE is not asserted a pending unmasked numeric exception exists SW ES 1 and the floating...

Page 47: ...l is defined for locked cycles only It is undefined for cycles which are locked SMI I The system management interrupt causes a system management interrupt request to be latched internally When the latched SMI is recognized on an instruction boundary the processor enters System Management Mode SMIACT O An active system management interrupt active output indicates that the processor is operating in ...

Page 48: ...ble J26 KBDCS Pull low Default AF5 INTR Pull high Default PCIVCC 3 3V AD5 NMI Pull high Default DRAMVCC 3 3V AC6 IGERR Pull low Default ISAVCC 5 0V H24 DBEW Pull low Default PPWR Normal mode R5 BOFF Pull low Pull low PPWR0 Selected N24 RTCAS Pull high Pull low Normal decode ISA mode R3 A20M Pull high Pull high Vcc3 AB14 PCICLK0 Pull low Default No MCACHE support B7 RSVD Pull low Default CPUVCC 3 3...

Page 49: ...MA10 MA11 MD63 MD62 GNT2 C BE1 C BE0 PLOCK DEV SEL MD61 MD60 MD59 MD58 MD57 VCC _PCI STOP GNT0 REQ2 CLK RUN MD56 MD55 MD54 MD53 VCC _DRAM GNT1 CPAR SERR PERR REQ0 MD52 MD51 MD50 MD49 MD48 REQ1 GNT3 REQ3 IRQ SER IRQ1 MD47 MD46 MD45 MD44 HD43 VCC _CORE IRQ 3 A IRQ 4 B IRQ 5 C IRQ 6 D MD42 MD41 MD40 MD39 VCC _DRAM CMD SEL ATB IRQ 7 E IRQ6 IRQ 9 F MD38 MD37 MD36 MD35 HD34 GND GND GND GND 5VREF IRQ 11 ...

Page 50: ...IGERR low when FERR is low IGERR AC6 I O 4mA Ignore Coprocessor Error Normally high IGERR will go low after FERR goes low and an I O write to Port 0F0h occurs When FERR goes high IGERR is driven high Strap option pin refer to Table 3 7 CPU Control Status CPUINIT AD6 O CPU Initialize a shutdown cycle or a low to high transition of I O Port 092h bit 0 will trigger CPUINIT If keyboard emulation is en...

Page 51: ...DA is active BOFF R5 O 4mA Back off This pin is connected to the BOFF input of the CPU Strap option pin refer to Table 3 7 CPURST R1 O 4mA Always CPU Reset This signal generates a hard reset to the CPU whenever the PWRGD input goes active RSMRST SYSCFG ADh 5 1 Resume Reset Generates a hard reset to the CPU on resuming from Suspend mode Host Power Control SMI AE5 O 4mA System Management Interrupt T...

Page 52: ... 3mA SYSCFG 11h 3 1 Column Address Strobe Bit 2 2nd copy START O 4mA SYSCFG 00h 5 1 Start If using the Sony cache module then this pin is connected to the START output from the Sony SONIC2 WP module If using the Sony cache module then TAG1 and TAG2 are connected to the START output from the module and TAG3 is connected to the BOFF output from the module The remaining TAG bits are unused TAG3 B9 I ...

Page 53: ...iming required for the functionality of this pin it can be programmed only as an output See Section 3 3 Programmable I O Pins on page 33 for more details 8 3 2 DRAM and PCI Interface Signal Set Signal Name Pin No Signal Type Drive Selected By Signal Description DRAM Interface RAS0 m E12 E12 O 8 12mA Cycle Multiplexed Row Address Strobe 0 Each RAS signal corresponds to a unique DRAM bank Depending ...

Page 54: ...WE input of the DRAMs SDWE SDRAM Write Enable This output is the write enable signal for SDRAM MA 11 0 Refer to Table 3 2 O 8 12mA Memory Address Bus Lines 11 through 0 Multiplexed row column address lines to the DRAMs Depending on the kind of DRAM modules being used these signals may or may not need to be buffered externally MA12 is optionally available instead of RAS3 or RAS4 MD 63 32 Refer to T...

Page 55: ...active by any PCI device that detects a system error condition Upon sampling SERR active FireStar generates a non maskable interrupt NMI to the 3 3V Pentium CPU PERR AE17 I O 4mA Party Error PERR may be pulsed by any agent that detects a parity error during an address phase or by the master or by the selected target during any data phase in which the AD 31 0 lines are inputs Upon sampling PERR act...

Page 56: ...9h 00h Programmable Input Output 9 See Section 3 3 Programmable I O Pins on page 33 for more derails Clock and Reset Interface RESET AC24 O 8mA System Reset When asserted this signal resets the CPU RESET is asserted in response to a PWRGD only and is guaranteed to be active for 1ms such that CLK and VCC are stable If RSTDRV is programmed to toggle in Suspend via SYSCFG 40h 0 so will RESET since RE...

Page 57: ...to any ISA or PCI interrupt through PCIDV1 B3h IRQD IRQ6 is a 5 0V tolerant input even when its power plane is connected to 3 3 V as long as the 5VREF pins of FireStar are connected to 5 0V IRQC IRQ7 AD20 I Programmable Interrupt Request E IRQ7 This input defaults to IRQ7 however it can be programmed to route onto any ISA or PCI interrupt through PCIDV1 B4h IRQ8 AE20 I PCIDV1 8Bh 00h Interrupt Req...

Page 58: ...ed to route onto any internal DRQ by programming PCIDV1 C1h 6 4 PIO28 I O 4mA PCIDV1 9Ch 00h Programmable Input Output 28 See Section 3 3 Programmable I O Pins on page 33 for more details DRQE DRQ5 L24 I PCIDV1 9Dh 00h Programmable DMA Request E DRQ5 The DRQ is used to request DMA service from the DMA controller This input defaults to DRQ5 however it can be programmed to route onto any internal DR...

Page 59: ...3 O Programmable DMA Acknowledge G DACK7 DACK is used to acknowledge DRQ to allow DMA transfer This input defaults to DACK7 however it can be programmed to route onto any internal DACK by programming PCIDV1 C3h 6 4 PPWR15 PCIDV1 C3h 6 4 100 Peripheral power control Line 15 Compact ISA Interface RSTDRV AC25 I O 4mA PCIDV1 8Fh 00h Reset Drive Active high reset signal to ISA bus devices RSTDRV can be...

Page 60: ... that it may latch data from the ISA data bus MWR is an output when the FireStar owns the ISA bus MWR is an input when an ISA master other than FireStar owns the ISA bus IDE1_DSC1 RACAS A20M strap option DCS1 Control for Secondary ISE Channel IOR AB24 I O 8mA I O Read IOR is the command to an ISA I O slave device that the slave may drive data on to the ISA data bus SD 15 0 The I O slave device mus...

Page 61: ... refresh An option to continuously drive this signal low during Suspend is also provided The internal pull up on this pin is disengaged in Suspend PPWR12 PCIDV1 C2h 0 1 Peripheral Power Control Line 12 SBHE W25 I O PCDIDV1 94h 00h System Byte High Enable When asserted SBHE indicates that a byte is being transferred on the upper byte SD 15 8 of the data bus SBHE is negated during refresh cycles SBH...

Page 62: ... Bit 1 for Secondary IDE Channel RTCWR N26 O 4mA Real Time Clock Write This pin is used to drive the write signal of the real time clock IDE1_DA2 Strap option pin refer to Table 3 7 I O RTCAS A20M strap option and PCIDV1 75h 7 1 Address Bit 2 for Secondary IDE Channel Power Management Unit Interface PPWRL AC23 O 4mA Default Power Control Latch This signal is used to control the external latching o...

Page 63: ...ut for the ATE Test Mode selection address See TMS Pin AB5 description SDCKE FS ACPI PCIDV1 52h 3 1 SDRAM Clock Enable in FireStar ACPI This signal is asserted to put the SDRAM into a Stop state The BIOS can program FireStar to assert this signal only in Suspend mode This pin is also an input for the ATE Test Mode selection address See TMS pin AB5 description TMS AB5 I O Test Mode Select An input ...

Page 64: ...Vss with 0V CNVss CNVss Pin controlling the operation mode of chip Connect this pin to Vss RESET Reset input Pin for the reset input of active L XIN Clock input Pin for the I O of clock generator Connect a ceramic resonator or crystal oscillator between XIN and XOUT When using external clock connect a clock generator to XIN and open XOUT A feedback resistor is incorporated XOUT Clock output P00 P0...

Page 65: ...OS and TTL DQ0 DQ7 I O port 8 bit data bus for the host CPU Input level can be switched between CMOS and TTL 9 4 Functional block diagram 49 P0 8 50 51 52 53 54 55 56 41 P1 8 42 43 44 45 46 47 48 33 P2 8 34 35 36 37 38 39 40 57 P3 8 58 59 60 61 62 63 64 20 P4 8 21 22 23 24 25 28 29 4 5 6 7 8 9 10 11 12 P5 4 13 14 15 16 17 18 19 2 3 P6 2 INT0 INT4 P0 8 A 30 31 XIN XOUT 32 VSS 27 RESET 1 VCC 26 CN V...

Page 66: ...elect up to 4 types of LCD panel initialization parameter for the VGA BIOS To use the above panel or TFT color set these parameters as follows Panel MAD5 MAD4 MAD3 Note TFT color H L H Set for UP5700 DUTY color H L L Reserved Not used L H L Reserved Not used L H H Reserved MAD4 and MAD5 can be set using the jumper on the main board For MAD3 you must design the relay board connected to the LCD mod ...

Page 67: ... TSENA 163 ICTENA 164 CFG10 165 CFG11 166 CFG12 167 CFG13 168 CFG14 169 CFG15 170 ROMD0 171 ROMD1 172 ROMD2 173 ROMD3 174 ROMD4 175 ROMD5 176 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 ROMD6 177 ROMD7 178 STNDBY 179 A2 ROMA0 180 A3 ROMA1 181 IVCC 182 A4 ROMA2 183 A5 ROMA3 184 IGND 185 A6 ROMA4 186 A7 ROMA10 187 A8 ROMA5 188 A9 ROMA11 189 A10 ROMA6 190 A11...

Page 68: ...e current cycle based on the memory or I O address which has been broadcast For VL Bus it is a direct output reflecting a straight address decode This pin is tri stated during Standby mode as are all other bus interface outputs 27 LCLK In Both Local Clock In VL Bus this pin is connected to the CPU 1x clock In CPU local bus interfaces it is connected to the CPU 1x or 2x clock If the input is a 2x c...

Page 69: ...08 I O High 40 D09 I O High 38 D10 I O High 37 D11 I O High 36 D12 I O High 35 D13 I O High 34 D14 I O High 33 D15 I O High 20 D16 I O High 19 D17 I O High 18 D18 I O High 17 D19 I O High 16 D20 I O High 15 D21 I O High 14 D22 I O High 13 D23 I O High 8 D24 I O High 7 D25 I O High 6 D26 I O High 5 D27 I O High 4 D28 I O High 3 D29 I O High 2 D30 I O High 1 D31 I O High Table 2 1 Bus Output Signal ...

Page 70: ... 31 during a read it indicates the master is prepared to accept data A data phase is completed on any clock when both IRDY and TRDY are sampled then asserted wait cycles are inserted until this occurs 24 TRDY S TS Low Target Ready Indicates the target s ability to complete the current data phase of the transaction During a read TRDY indicates that valid data is present on AD0 31 during a write it ...

Page 71: ...us To avoid abnormal Vcc current due to a floating input for a PCI Bus use a 10K resistor to ground to pull this pin low 51 AD00 I O High PCI Address Data Bus Address and data are multiplexed on the same pins A bus transaction consists of an address phase followed by one or more data phases both read and write bursts are allowed by the bus definition The address phase is the clock cycle in which F...

Page 72: ... video capture 99 HREF In High Horizontal reference input for video capture 156 RASA RASAB0 Out Low RAS for DRAM A or bank 0 in 2MB configurations 123 RASB RASAB1 Out Low RAS for DRAM B or bank 1 in 2MB configurations 101 RASC VRDY Out Low RAS for DRAM C or color key input from external PC Video source or VAFC Video System Ready input KEY In High 160 CASAL WEAL Out Low CAS for the DRAM A lower byt...

Page 73: ...erface Note that this configuration also provides additional panel outputs so that a video input port may be implemented along with a 24 bit true color TFT panel TFT panels never need DRAM C In VAFC interface mode pin 106 is the VAFC Enable Video input The external VAFC interface drives this pin low to indicate data input on the VP0 15 EVID is ignored essertially reserved in the 65550 VAFC data is...

Page 74: ...TN Color Color Color Color 65550 SS DD DD TFT TFT TFT HR STN SS STN SS STN DD STN DD STN DD Pin Pin Name 8 bit 8 bit 16 bit 9 12 16 bit 18 24 bit 18 24 bit 8 bit X4bP 16 bit 4bP 8 bit 4bP 16 bit 4bP 24 bit 71 P0 UD3 UD7 B0 B0 B00 R1 R1 UR1 UR0 UR0 72 P1 UD2 UD6 B1 B1 B01 B1 G1 UG1 UG0 UG0 73 P2 UD1 UD5 B2 B2 B02 G2 B1 UB1 UB0 UB0 74 P3 UD0 UD4 B3 B3 B03 R3 R2 UR2 UR1 LR0 75 P4 LD3 UD3 B4 B4 B10 B3...

Page 75: ...rved Reserved For compatibility with the 65545 this pin formerly Crystal Out or XTLAO must be disconnected In addition pin 150 must be pulled down on reset The 65545 no longer supports the internal oscillator option 205 CVCC0 VCC Analog power and ground pins for noise isolation for the internal clock synthesizer Must be the same as VCC for internal logic VCC GND pair 0 and VCC GND pair 1 pins must...

Page 76: ...ion II Video Input Module NTSC PAL Video Input 16 bit Video Decoder w o Scaling Video Input Module Video Decoder w o Scaling 16 bit PCI Bus Maxer 32 Bit 32 Bit System Bus RGB to NTSC 32 Bit RGB TV Monitor CRT Monitor 24 Color STN TFT 2 Meg Shared Frame Buffer HiQV32 CHIPS TM R 32 Bit HiQV32TM Memory RGB YUVa YUVb Memory Controller 64 bit Graphlcs Engine YUV to RGB Color Key Zoom RGB YUV Analog RGB...

Page 77: ... bit 4 of the Parallel Port Control Register If EPP or ECP mode is enabled this output is pulsed low then released to allow sharing of interrupts RESET 57 IS Reset This active high signal resets the M5113 and must be valid for 500 ns minimum In M5113 the falling edge of reset latches the jumper configuration The jumper select lines must be valid 50 ns prior this edge Floppy Disk Interface RDATAJ 1...

Page 78: ... and latched during reset active DTR2J S2CF1 93 O4 I Data Terminal Ready This active low output is for secondary serial port Handshake output signal notifies modem that the UART is ready to establish data communication link This signal can be programmed by writing to bit 0 of Modem Control Register MCR The hardware reset will clear the DTRJ signal to inactive mode high Forced inactive during loop ...

Page 79: ...T 59 I Printer Selected Status This active high output from the printer indicates that it has power on Bit 4 of the Printer Status Register reads the SLCT input ERRORJ 75 I Error This active low signal indicates an error condition at the printer PD0 PD7 71 68 66 63 I O20 Port Data This bi directional parallel data bus is used to transfer information between CPU and peripherals IOCHRDY 100 OD24 IOC...

Page 80: ...mA 0 4 V 11 4 Functional block diagram CLK1 CLK2 Clock Gen SERIAL CLOCK Host CPU Interface IORJ IOWJ AEN A0 A9 A0 A7 FDRQ DACKJ PINTR3 TC UR2IRQB UR2IRQA UR1IRQB UR1IRQA PINTR1 PINTR2 FINTR RESET DFRQA DRQB DACKA DACKB A10 IOCHRDY PWRGD Power Management DATA BUS ADDRESS BUS Configuration Registers 765A Compatible Floppy Disk Controller Core Data Separator with Write Precompensa tion WDATA WCLOCK R...

Page 81: ...asters into consideration After power off POFF 0 is detected if the power down of DC 5V PWRGOOD 0 is detected or 200ms elapsed PWRGD signal is automatically set to 0 by hardware Applications must be completely shunted before the PSC2 automatically shutdowns When resetting using the software enabling the shutdown enable bit bit 0 of special system register 1 allows hardware reset After enabling thi...

Page 82: ... and SHEN1 2 signals shift enable signal must be prepared as CKDC interface However SHEN1 2 are used in the PSC2 as dedicated signal pins inputting interrupt events SCKF is outputted to SCK pin without the logic changed and preset to 1 by RESET The serial data is in the form of LSB first SCKF operates with synchronized with SCK and the operation speed de pends on the speed of CPU because the shift...

Page 83: ...turn signals to scan keys 16 strobe signals are generated from the 4 strobe signals using 2 sets of 74LS138 external circuit The mode key or clerk key etc gives its return signal to the PSC2 respectively Data from each key can be read at any timing In addition when the status of key data changes an maskable interrupt can be generated 12 4 Pin assignment 156 155 154 153 152 151 150 148 148 147 146 ...

Page 84: ...M4 6 DTR 50 I DSR2 RS 232 COM4 6 DSR 51 O RTS2 RS 232 COM4 6 RTS Pin No I O Signal name Function 52 I CTS2 RS 232 COM4 6 CTS 53 I DCD2 RS 232 COM4 6 DCD 54 I RI2 RS 232 COM4 6 RI 55 GND 56 O TXD1 RS 232 COM3 5 TXD 57 I RXD1 RS 232 COM3 5 RXD 58 O DTR1 RS 232 COM3 5 DTR 59 I DSR1 RS 232 COM3 5 DSR 60 O RTS1 RS 232 COM3 5 RTS 61 I CTS1 RS 232 COM3 5 CTS 62 I DCD1 RS 232 COM3 5 DCD 63 I RI1 RS 232 CO...

Page 85: ... SA22 Pin No I O Signal name Function 155 I SA23 ISA BUS SA23 156 GND 157 O PIRQ3 INTERRUPT REQUEST 3 to CPU 158 O PIRQ4 INTERRUPT REQUEST 4 to CPU 159 O PIRQ9 INTERRUPT REQUEST 8 to CPU 160 O PIRQ10 INTERRUPT REQUEST 10 to CPU 161 O PIRQ11 INTERRUPT REQUEST 11 to CPU 162 O PIRQ15 INTERRUPT REQUEST 15 to CPU 163 O PWRGD POWER GOOD to CPU 164 GND 165 VDD 166 O PRAS0 STD PS RAM WORD CHIP SELECT 0 16...

Page 86: ...imum EDO page mode Refresh 4096 cycles 128ms 31 25us CBR CAS before RAS refresh Row Column 12 8 asymmetric Bank 0 14 2 Option Memory 144 pin small outline DIMM Size 8 16 32 MB 3 3V single power source 0 3V Access time 60ns Maximum EDO page mode Refresh 15us CBR CAS before RAS refresh Bank 1 15 BIOS ROM 15 1 Outline Sharp s LH28F004SUT NC80 Composed of erase blocks divided into 16KB even blocks 5V ...

Page 87: ...rea to be accessed is determined by inputting ad dress signals from the ISA bus The RAM disk area is base address 4000h 7FFFh with the size of 16KB 18 3 Bank Switch Chip select and bank switch are performed by issuing address signal BA0 5 and chip select signal PRAS 0 2 from the PSC2 19 Analog Touch Panel 19 1 Outline The analog touch panel is controlled by Fujitsu s control IC N010 0559 V021 and ...

Page 88: ...20 4 Shutdown Control The power switch of UP 5700 is used to switch the ON state and stand by state of terminal When starting up the terminal the power switch is necessary to be set ON When the power switch is set to the position of stand by mode the power source unit stops automatically If HOP1 pin of the PSC2 is held PHOLD 1 by the software the power source unit continues to run until the softwa...

Page 89: ... and the number of characters in a card corresponding to each standard is as follows JBA JIS 2 type 72 characters maximum 8 bits a character ABA JIS 2 type second track 40 characters maximum 5 bits a character IATA JIS 1 type first track 79 characters maximum 7 bits a character 2 FIFOs are prepared independently to 2 channels of interface These FIFOs can be read simultaneously when connected to a ...

Page 90: ...ignal Function I O 1 RS Request to Send O 2 ER Data terminal Ready O 3 SD Send Data O 4 SG 5V Signal Ground 5V 5 SG Signal Ground 6 RD Receive Data I 7 DR Data set Ready I 8 CS Clear to Send I Note 5V can be supplied to pin 4 by switching with a 0W resister By default pin 4 is used as SG 3 COM4 6 RJ45 Pin No Signal Function I O 1 RS Request to Send O 2 ER Data terminal Ready O 3 SD Send Data O 4 S...

Page 91: ...LD signal overvoltage protection against power abnormality and overcurrent protection which protects the power from an overload 2 Block diagram PHSNS 5V 12V GND 12V GND ACL RLY1 PHOLD GND Regulator Regulator N F section PHSNS Detector section Convertor section Output monitor Overvoltage protection PHOLD circuit Rectifying section Temperature protection Rectifying section Control section Rectifying...

Page 92: ...output capacitor 3 2 Control section 5V By repetition of operations in 3 1 a voltage is generated in the secondary side 5V is divided by R16 R27 and R18 to input to IC1 R pin IC1 always monitors the divided voltage When the output voltage becomes higher than 5V the divided voltage also tries to be higher Then IC1 judges it as a rise in the output voltage to light photo coupler PC1 through R23 When...

Page 93: ...es HIGH When SW1 is turned off PC2 turns off to drive the PHSNS signal LOW 3 6 PHOLD signal This signal is provided from the main PWB When this signal is HIGH 5V Q5 turns on to turn on relay RLY1 turning off SW1 The AC input voltage is supplied through RLY1 to stabilize the output voltage When PHOLD signal becomes LOW the relay turns off to stop the power 8 13 14 9 10 D16 FMB26L C20 330µF 35V PW P...

Page 94: ...r thermistor TH1 is inserted to limit the rush current 3 10 Line filter To prevent against external noises or noises from the power source itself the line filter is composed of L1 L2 C1 C2 C3 C4 C13 C15 and C16 to reduce noises 3 11 Temperature protection Thermostat TS1 is attached to the heat radiating plate in the power source unit When the internal temperature rises because of fan lock or outpu...

Page 95: ...tputs stop refer to the 5V troubleshooting 1 When the voltage between IC4 1 3 pin is 14V or lower 12V is not supplied 2 D17 open may be the cause 1 IC4 trouble may be the cause NO YES NO YES START OK YES NO Are 5V and 12V supplied normally Is the voltage at IC3 1 3 pin 12 5V or more Is 12V supplied Repair Repair Repair NO YES NO YES START OK YES NO Are 5V and 12V supplied normally Is the voltage a...

Page 96: ... supplied 1 If 5V and 12V are not supplied PHSNS signal is not sup plied 1 R3 4 18 19 or PC2 open may be the cause 2 D7 short may be the cause 1 Q4 short may be the cause NO YES NO YES START OK YES NO Are 5V and 12V supplied normally Is the voltage across C26 13V or more Is ALC of about 5V supplied Repair Repair Repair NO YES NO YES START OK YES NO Are 5V and 12V supplied normally Is the voltage a...

Page 97: ...B1 DTZ5 1A 5V R38 1K Q4 DTC114EUA RN1302 Q5 DTC114EUA RN1302 4 2 8 11 12 T1 P1165 7 13 14 6 9 10 D16 FMB26L D10 SF10SC4 Q3 2SK2512 K2312 R37 1K R20 10K 8 1 2 3 4 5 6 7 IC1 SR101 R36 56 C20 330µF 35V PW PY LXJ D15 1SS270A 3 2 1 IC3 C21 100µF 35V PW PY C30 C31 C32 C33 2200µF 10V PW PY x 4 TS1 67F110 L4 SBC6 4R7 802 C22 104K R22 330 C18 C19 104K 100µF 10V PW PY 2 3 12 8 9 10 12V 12V PH SNS 5V 5V 5V G...

Page 98: ...9 HZM5 1B1 RD5 1SB1 DTZ5 1A 5V R38 1K Q4 DTC114EUA RN1302 Q5 DTC114EUA RN1302 4 2 8 11 12 T1 P1165 7 13 14 6 9 10 D16 FMB26L D10 SF10SC4 Q3 2SK2512 K2312 R37 1K R20 10K 8 1 2 3 4 5 6 7 IC1 SR101 R36 56 C20 330µF 35V PW PY LXJ D15 1SS270A 3 2 1 IC3 C21 100µF 35V PW PY C30 C31 C32 C33 2200µF 10V PW PY x 4 TS1 67F110 L4 SBC6 4R7 802 C22 104K R22 330 C18 C19 104K 100µF 10V PW PY 2 3 12 8 9 10 12V 12V ...

Page 99: ...l fluctuation 150mV 600mV Note 1 1200mV Ripple voltage 150mV or less 150mV or less 150mV or less Spike voltage 150mV or less 200mV or less 200mV or less Overcurrent protection System with IC3 with IC4 Operating value 6 5A or more Short current 12A or less Overvoltage protection System Oscillation stop Operating value 6V or more Instantaneous service interruption protection 20ms or less 20ms or les...

Page 100: ...nu format On numpad press 7 and period at same time After 1 long beep menu will be displayed System will reset automatically after setup is terminated 3 Setup Outline in Menu Format Setup in menu format is not required during normal operation Use only in case such as checking contents of setup during maintenance or modifying setup contents required due to system operation 1 Key assignments Followi...

Page 101: ...red in conventional memory at displayed address nnnn K Shadow RAM Failed at offset nnnn W R error occured in Shadow RAM at displayed address Failing Bits nnnn Bit missing error occured by memory test Message displayed by Extended RAM test position Message Error meaning nnnn K Extended RAM Failed at offset nnnn W R error occured in extended memory at displayed address Failing Bits nnnn Bit missing ...

Page 102: ...tion the bottom pressing point of touch panel device and to align the LCDs display area The adjustment value returned from this utility is saved in EEPROM inside touch panel controller This will save the data even if the power is shut down Function At shipment of UP 5700 the touch panel position has already ad justed To adjust it use the touch pen of K PDA Keyboard enhanced Per sonal Digital Assis...

Page 103: ...20 16 AD21 15 AD22 14 AD23 13 AD24 8 AD25 7 AD26 6 AD27 5 AD28 4 AD29 3 AD30 2 AD31 1 MCD0 106 MCD1 Y0 107 MCD2 Y1 109 MCD3 Y2 110 MCD4 Y3 111 MCD5 Y4 112 MCD6 Y5 113 MCD7 Y6 114 MCD8 Y7 115 MCD9 UV0 116 MCD10 UV1 117 MCD11 UV2 118 MCD12 119 MCD13 UV3 120 MCD14 UV4 121 MCD15 UV5 122 CA0 P16 90 CA1 P17 91 CA2 P18 92 CA3 P19 93 CA4 P20 94 CA5 P21 95 CA6 P22 96 CA7 P23 97 CA8 VREF 98 HREF 99 RASC 101...

Page 104: ...pin SSOP VCC5 RTCRD RTCWR RTCAS IRQ8 RTCRD RTCAS RTCWR IRQ8 2 1 R251 10K RTC SD4 SD3 SD2 SD1 SD0 RSTDRV RCL TP1 TP2 Y1 32 768kHz 2 1 C200 1000p 2 1 C199 0 1u 12 13 11 IC23D 74HC08 2 1 C196 0 1u VCC2 12 13 11 IC22D 74HC00 9 10 8 IC22C 74HC00 VCC5 C14 0 1u C15 100u 10V Q13 Si9430 2 1 R3 150KF 2 1 R4 140KF C17 150u 6 3V OS C18 2 1 R2 1 2W 0 033 F D4 SFPB72 1 2 L3 39uH C30 150u 6 3V OS C31 150u 6 3V O...

Page 105: ...4 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 CN14 WR 200S VFW30 1 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PWRGD VCC3 SERR PERR RTCWR RTCRD SERR PERR DDRQ RTCWR RTCRD DCS3 DCS1 DDAK DA2 DA1 DA0 DRD DWR CPAR CPAR RTCAS RTCAS DBEW VCC3 MSTR CHCK NOWS PCICL...

Page 106: ... BA1 180 BA0 181 MROS 184 FROS0 185 FROS1 186 FROS2 187 FROS3 188 FROMP 189 FROMWP 190 IS6 191 TXD1 56 RXD1 57 DTR1 58 DSR1 59 RTS1 60 CTS1 61 DCD1 62 RI1 63 TXD2 47 RXD2 48 DTR2 49 DSR2 50 RTS2 51 C T S 2 5 2 D C D 2 5 3 R I 2 5 4 T X D 3 2 8 R X D 3 2 9 D T R 3 3 0 D S R 3 3 1 R T S 3 3 2 C T S 3 3 3 D C D 3 3 4 R I 3 3 5 T X D 4 3 7 R X D 4 3 8 D T R 4 3 9 D S R 4 4 0 R T S 4 4 1 C T S 4 4 2 D ...

Page 107: ...OR IRQ12 IRQ1 KBDCS IOW IRQ1 IRQ12 IOR IOW KBDCS RSTDRV RSTDRV VCC5 R179 10K R173 33 C124 330p R248 0 SA2 KBDATA KBCLK MSDATA MSCLK KRTN0 KRTN1 KRTN2 KSTB11 KRTN3 KRTN4 KRTN5 KRTN6 KRTN7 1 2 3 C148 C149 C150 C151 C152 C153 C154 C147 47pX8 C125 C126 C138 X1 CSTCC4 00MG VCC5 VCC5 KRTN 0 7 KRTN 0 7 4 6 2 1 7 5 3 9 8 CN20 87123 0630 MOLEX C139 47p x 4 1 8 2 7 3 6 4 5 BR23 10Kx4 1 8 2 7 3 6 4 5 FB12 AC...

Page 108: ... SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 BA0 BA1 BA2 BA3 BA4 BA5 PRAS0 VRAM PRFSH SD2 SD3 SD4 SD5 SD6 SD7 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 BA0 BA1 BA2 BA3 BA4 BA5 PRAS0 C209 0 1uF C9 10uF 10V OS C207 100pF C206 100pF VRAM SD10 SD11 SD12 SD13 SD14 SD15 FROMBY FROMWP FROMRP FROS2 FROS1 MROS BA18 FROMWP FROMRP FROS2 FROS1 MROS BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BA8 BA18 PRFSH PRAS2 PRAS1 ...

Page 109: ...D5 41 D6 43 D7 45 D8 29 D9 31 D10 33 D11 35 D12 40 D13 42 D14 44 D15 A 1 46 GND 48 GND 47 GND 36 GND 26 GND 25 GND 12 VCC 37 VCC 38 IC30 LH53V32500T SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SD0 SD1 SD2 SD4 SD5 SD6 SD7 SD8 SD9 Socket BA0 BA1 BA2 BA3 BA4 SD3 SD10 SD11 SD12 SD13 SD14 SD15 A0 32 A1 28 A2 27 A3 26 A4 25 A5 24 A6 23 A7 22 A8 20 DQ15 52 DQ0 33 DQ1 35 DQ2 38 DQ3 40 DQ4 ...

Page 110: ...E 60 SLCT 59 ERRJ 75 SLCTINJ 73 INITJ 74 AUTOFDJ 76 STROBEJ 77 PD0 71 PD1 70 PD2 69 PD3 68 PD4 66 PD5 65 PD6 64 PD7 63 I R Q 5 P I N T R 2 A D R 9 4 D T R 2 J 9 3 D T R 1 J 8 3 R T S 2 J 9 1 R T S 1 J 8 1 T X D 2 I R T X 8 9 TXD1 79 DRVDEN0 1 I R Q I N P D I R 9 9 D A C K 3 J 9 6 MTR1J 5 MTR0J 2 A 1 0 9 7 D R Q 3 9 8 DRV1J 3 DRV0J 4 STEPJ 8 DIR 7 HDSELJ 11 WDATAJ 9 WGATEJ 10 I R Q 7 3 9 I R Q 6 4 ...

Page 111: ... B30 80 B31 81 D1 82 D2 83 D3 84 D4 85 D5 86 D6 87 D7 88 D8 89 D9 90 D10 91 D11 92 D12 93 D13 94 D14 95 D15 96 D16 97 D17 98 D18 99 E1 50 F1 100 CN9 176380 4 AMP R200 1K R207 10K AEN IOCHRDY IOCHRDY AEN VCC5 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD 0 15 SD 0 15 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 R117 1K C219 1000pF S D 0 S D 1 S D 2 S D 3 S D 5 S D 4 S D 6 S D 7 SD 0 15 VCC5 1 8 2...

Page 112: ...R1 SD1 RD1 CD1 COM1 CN GND CI1 ER1 CS1 SD1 RS1 RD1 DR1 D SUB CABLE 1 2 3 4 5 6 7 8 9 5 9 4 8 3 7 2 6 1 D SUB 9PIN CONNECTOR CI2 CS2 RS2 GND ER2 SD2 RD2 COM2 CN CD1 1 2 3 4 5 6 7 8 9 CN8 MLX 53014 0910 SD2 RD2 ER2 CI2 FB101 BLM31 FB129 BLM31 FB128 BLM31 FB130 BLM31 FB131 BLM31 PVCC5 1 2 F3 ICP S0 5 S2 SSSS312 12V VCC5 10 8 9 IC9C 75189 14 15 12 13 10 11 8 1 16 3 2 5 4 7 6 9 IC2 MC145406 C101 0 1uF ...

Page 113: ...S3 CS3 R147 100K R146 3 3K R145 100K R144 3 3K FB116 BLM31 FB113 BLM31 FB117 BLM31 FB112 BLM31 COM3 5 CN SD3 RD3 DR3 CS3 GND PVCC5 J1 COM4 6 CN RS4 ER4 SD4 RD4 DR4 CS4 GND GND 1 2 3 4 5 6 7 8 CN5 EMJ88HOPL SD4 RD4 ER4 DR4 RS4 R143 100K R142 3 3K R141 100K R140 3 3K R139 100K FB109 BLM31 FB108 BLM31 FB110 BLM31 FB107 BLM31 FB111 BLM31 12V VCC5 R156 1 2K R155 1 2K C118 220pF C119 220pF 14 15 12 13 1...

Page 114: ... 4 5 6 7 8 CN6 EMJ88HOPL PVCC5 SD FB104 BLM31 12V VCC5 POLE DISPLAY 14 15 12 13 10 11 8 1 16 3 2 5 4 7 6 9 IC7 MC145406 C112 0 1uF TXD8 TXD8 DTR8 DSR8 DSR8 DTR8 12V C116 220pF R153 1 2K ER DR R137 100K R136 3 3K FB105 BLM31 FB103 BLM31 SD DR POLE 12 16 9 12 ...

Page 115: ...MCR CN FB150 FB148 FB147 BLM31 X6 FB151 PVCC5 1 2 3 4 5 6 7 8 CN18 5045 0810 13 12 IC18F 4069 11 10 IC18E 4069 9 8 IC18D 4069 5 6 IC18C 4069 3 4 IC18B 4069 FB149 FB152 R234 4 7KX6 R231 R229 R224 R226 R228 R227 10K R225 10K R230 10K R232 10K R223 10K CLS1 CLS2 RDD1 RCP1 RDD2 RCP2 1 2 IC18A 4069 R233 10K 13 16 9 13 ...

Page 116: ... 0x4 1 8 2 7 3 6 4 5 BR4 0x4 R178 1K VCC5 1 8 2 7 3 6 4 5 BR6 1Kx4 1 8 2 7 3 6 4 5 BR7 1Kx4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CN11 53047 1510 MOLEX 1 2 3 4 5 6 7 8 9 10 CN10 53047 1010 MOLEX PERROR PACK PBUSY PPE PSLCT PP1 PP3 PP5 PP7 1 8 2 7 3 6 4 5 BR3 0x4 R104 22 1 8 2 7 3 6 4 5 BR2 0x4 PAUTOFD PINIT PSLCTIN 14 16 9 14 ...

Page 117: ...Q4 DTC114YK DRSNS1 12V VCC5 DRW CN1 FB3 C66663 2 3 1 Q1 DTA144EK R150 6 8K C111 0 1uF C109 0 1uF R152 6 8K 2 3 1 Q2 DTA144EK 4 5 10 IC4B 4AC16 1 2 3 CN3 5046 03A DS 12V R151 2 7K R130 1K C110 1000pF R129 47K DRSNS0 DRSNS1 FB4 C66663 LINK IDE SCH MCRIF SCH PSC2 SCH POWER SCH PSRAM SCH ROM SCH RS1_2 SCH RS3_4 SCH SLOT SCH SUPERIO SCH PARALLEL SCH POLEDISP SCH 15 16 9 15 ...

Page 118: ... 2 3 4 5 6 7 8 9 10 11 12 CN25 GIL G 12P S3T2 E ACL PVCC5 1 2 F1 3 15A 125V VCC3 C212 0 1uF L5 3 5uH C28 10uF 10V OS C220 0 1uF VRAM VCC5 PHOLD PHSNS D8 1SS322 Q103 SI9410DY C218 0 1uF L4 10uH 3A Q104 SI9410DY R246 1 2W 0 025 D106 SFPB72 C19 220uF 6 3V OS VCC5 C26 47uF 25V C216 0 1uF C213 0 1uF SS 1 BST 14 LX 15 PGND 12 CSH 8 CSL 9 DH 16 DL 13 GND 4 REF 3 SHDN 6 SKIP 2 V 1 0 V L 1 1 F B 7 S Y N C ...

Page 119: ...C MKey IDE 6 A DA1 3 VGA CONNECTOR 4 C 5 RTC MKey IDE 6 A DA2 3 VGA CONNECTOR 4 C 5 RTC MKey IDE 6 A DAK 0 3 VGA CONNECTOR 3 B 9 SLOT 6 B DAK 1 3 VGA CONNECTOR 3 B 8 SUPER I O 8 A 9 SLOT 6 C DAK 2 3 VGA CONNECTOR 3 B 8 SUPER I O 6 A 9 SLOT 6 B DAK 3 3 VGA CONNECTOR 3 B 8 SUPER I O 7 D 9 SLOT 6 C DAK 4 3 VGA CONNECTOR 3 B DAK 5 3 VGA CONNECTOR 3 B 9 SLOT 6 A DAK 6 3 VGA CONNECTOR 3 B 9 SLOT 6 A DAK...

Page 120: ...TOR 5 C 4 PSC2 3 A 8 SUPER I O 1 B PWRGOOD 4 PSC2 8 C 6 PS RAM 8 B R12 8 SUPER I O 2 D 10 RS 1 2 DRIVER RECEIVER 8 B RCP1 4 PSC2 7 D 13 MCR I F 3 C RCP2 4 PSC2 7 D 13 MCR I F 3 B RDD1 4 PSC2 7 D 13 MCR I F 3 C RDD2 4 PSC2 7 D 13 MCR I F 3 B RFOS0 4 PSC2 2 C RFSC 3 VGA CONNECTOR 5 A RFSH 4 PSC2 8 C 9 SLOT 6 C RI1 8 SUPER I O 2 C 10 RS 1 2 DRIVER RECEIVER 8 D ROMCS 7 ROM 8 C RSTDRV 3 VGA CONNECTOR 2...

Page 121: ...3 C SERR 1 VGAC T655550 8 C 3 VGA CONNECTOR 3 C SHEN 4 PSC2 3 A 5 RTC MKey IDE 2 B SIOCS 4 PSC2 7 D 8 SUPER I O 7 C SMRD 3 VGA CONNECTOR 5 A 9 SLOT 6 C SMWR 3 VGA CONNECTOR 5 A 9 SLOT 6 C ST0 4 PSC2 7 D 5 RTC MKey IDE 2 D ST1 4 PSC2 7 D 5 RTC MKey IDE 2 D ST2 4 PSC2 7 D 5 RTC MKey IDE 2 D ST3 4 PSC2 7 D 5 RTC MKey IDE 2 D STH1 4 PSC2 3 A 5 RTC MKey IDE 2 B STNDBY 1 VGAC T655550 6 D 1 VGAC T655550 ...

Page 122: ...D IRQ6 AF19 IRQE IRQ7 AD20 PIO11 IRQ8 AE20 IRQF IRQ9 AF20 IRQG IRQ10 AB22 IRQH IRQ11 AC21 PIO12 IRQ12 AD21 PIO13 IRQ14 AE21 SIN IRQ15 AF21 SOUT IRQSER AE18 PIO25 DRQA DRQ0 M24 PIO26 DRQB DRQ1 M25 PIO27 DRQC DRQ2 M26 PIO28 DRQD DRQ3 L23 PIO29 DRQE DRQ5 L24 PIO30 DRQF DRQ6 L25 PIO31 DRQG DRQ7 L26 DACK7 J23 DACK6 J22 DACK5 K26 DACK3 K25 DACK2 K24 DACK1 K23 DACK0 K22 S D 0 S D 1 S D 2 S D 3 S D 4 S D ...

Page 123: ...SD 0 15 RTCRD DCS3 DCS1 DDAK DA2 DA1 DA0 DRD DWR DCS3 DCS1 DDAK DA2 DA1 DA0 DRD DWR RTCAS RTCAS DBEW DBEW MSTR CHCK NOWS VCC3 MSTR CHCK NOWS PCICLK1 PCICLK1 OSC32K OSC14M CPUCLK PCICLK CPUCLK PCICLK VCC3 FS14M FS14M FS32K FS32K CPU 60MHz PCI 30MHz Suspend 32KHz Only R34 FSCLK FSCLK 2 1 R34 33 2 1 R35 33 1 8 2 7 3 6 4 5 BR14 22x4 1 8 2 7 3 6 4 5 FB23 ACA3216M4 300 2 1 C55 2 1 C38 0 1u VCC3 2 1 C39 ...

Page 124: ... 1 5 V C C 3 E 2 1 V C C 3 E 2 7 V C C 3 A J 1 1 V C C 3 A J 1 9 V C C 3 A J 2 9 V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S V S S B...

Page 125: ...30 135 D31 137 A10 111 A11 106 A12 110 CAS2 115 VCC 11 VCC 12 VCC 27 GND 1 GND 2 GND 21 GND 22 GND 35 GND 36 GND 55 GND 56 GND 75 GND 76 GND 91 GND 92 GND 107 GND 108 GND 119 GND 120 GND 139 GND 140 VCC 28 VCC 45 VCC 46 VCC 63 VCC 64 VCC 81 VCC 82 VCC 101 VCC 102 VCC 113 VCC 114 VCC 129 VCC 130 VCC 143 VCC 144 D32 4 D33 6 D34 8 D35 10 D36 14 D37 16 D38 18 D39 20 D40 38 D41 40 D42 42 D43 44 D44 48 ...

Page 126: ...OR 5 B DAK 2 1 ATCL 1 D 2 CONNECTOR 5 B DAK 3 1 ATCL 1 D 2 CONNECTOR 5 B DAK 4 1 ATCL 1 D 2 CONNECTOR 5 B DAK 5 1 ATCL 1 D 2 CONNECTOR 5 B DAK 6 1 ATCL 1 D 2 CONNECTOR 5 B DAK 7 1 ATCL 1 D 2 CONNECTOR 5 B DBEW 1 ATCL 6 A 1 ATCL 1 C 2 CONNECTOR 5 C DCS1 1 ATCL 1 C 2 CONNECTOR 5 C DCS3 1 ATCL 1 C 2 CONNECTOR 5 C DDAK 1 ATCL 1 C 2 CONNECTOR 5 C DDRQ 1 ATCL 1 C 2 CONNECTOR 5 C DEVSEL 1 ATCL 1 B 2 CONN...

Page 127: ... 8 D MA8 1 ATCL 8 A 4 DRAM 8 D MA9 1 ATCL 8 A 4 DRAM 8 D MD0 1 ATCL 8 A 4 DRAM 8 D MD1 1 ATCL 8 A 4 DRAM 8 D MD10 1 ATCL 8 A 4 DRAM 8 D MD11 1 ATCL 8 A 4 DRAM 8 D MD12 1 ATCL 8 A 4 DRAM 8 D MD13 1 ATCL 8 A 4 DRAM 8 D MD14 1 ATCL 8 A 4 DRAM 8 D MD15 1 ATCL 8 A 4 DRAM 8 D MD16 1 ATCL 8 A 4 DRAM 8 D MD17 1 ATCL 8 A 4 DRAM 8 D MD18 1 ATCL 8 A 4 DRAM 8 D MD19 1 ATCL 8 A 4 DRAM 8 D MD2 1 ATCL 8 A 4 DRAM...

Page 128: ...1 ATCL 1 D 2 CONNECTOR 5 C SD3 1 ATCL 1 D 2 CONNECTOR 5 C SD4 1 ATCL 1 D 2 CONNECTOR 5 C SD5 1 ATCL 1 D 2 CONNECTOR 5 C SD6 1 ATCL 1 D 2 CONNECTOR 5 C SD7 1 ATCL 1 D 2 CONNECTOR 5 C SD8 1 ATCL 1 D 2 CONNECTOR 5 C SD9 1 ATCL 1 D 2 CONNECTOR 5 C SERR 1 ATCL 1 B 2 CONNECTOR 5 D SMI 1 ATCL 8 C 4 CPU 5 A 4 CPU 2 B SMIACT 1 ATCL 8 C 4 CPU 3 A 4 CPU 5 A 4 CPU 2 B SMRD 1 ATCL 1 C 2 CONNECTOR 8 A SMWH 1 AT...

Page 129: ...53X7 1 2 3 4 5 6 7 8 CN1 MLX 53015 0810 X4 X5 X6 WMF CN 9 8 1 0 IC4C 74LS125 12 11 1 3 IC4D 74LS125 FB5 BLM31 FB6 BLM31 FB7 BLM31 X1 X2 X3 2 3 1 IC3A 74LS125 5 6 4 IC3B 74LS125 9 8 1 0 IC3C 74LS125 FB2 BLM31 FB3 BLM31 FB4 BLM31 KEY RETURN S2 S1 VCC5 VCC5 R11 3 3K R12 2 2K S2 S1 S0 12V ENABKT VR1 VR2 INV CN 12V 1 2 3 4 5 CN3 MLX 53015 0510 1 2 3 4 5 6 7 8 CN5 MLX 5597 08APB VCC5 R10 10K 3 2 1 8 4 I...

Page 130: ... 64 OS1 63 CSEL 14 S P 2 MOD0 20 MOD1 21 17 RXINT 16 TXD 57 UCKI 58 UCKO 59 VCC 56 VSS 49 VSS 24 AVCC 11 AVR 12 AVSS 13 XO 22 XI 23 IC6 MB89635R Q4 DTA124EKA Q3 DTC124TKA Q2 DTA124EKA Q1 DTA124EKA VCC5 VCC5 VSS T PRES 4 5 6 3 2 8 7 IC5 S 29390AF E PROM 2 VCC5 R5 R3 10KX3 C1 0 1uF R4 AVCC AVCC AVSS TXD9 RXD9 C6 C7 C4 100pFX3 C3 0 1uF C2 680uF 16V C5 33uF 16V C103 0 1uF AVSS VCC5 C9 C10 C102 680pF Q...

Page 131: ... 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CN8 04 6214 030 010 800 CK Vsync R0 R2 R4 GND G1 G3 G5 B0 B2 B4 GND VCC PCK PVS PR0 PR2 PR4 PG1 PG3 PG5 PB0 PB2 PB4 to TFT_PANEL SMAD3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 CN10 04 6214 030 010 800 PG4 PG3 PG2 PG1 PG0 GND PR5 PR4 PR3 PR2 PR1 PR0 GND PVS PHS PCK SMAD3 from VGAC 3 3 L...

Page 132: ...I F 5 C PHS 2 LCD RELAY I F 6 B PR0 2 LCD RELAY I F 3 C PR0 2 LCD RELAY I F 6 B PR1 2 LCD RELAY I F 5 C PR1 2 LCD RELAY I F 6 B PR2 2 LCD RELAY I F 3 C PR2 2 LCD RELAY I F 6 B PR3 2 LCD RELAY I F 5 C PR3 2 LCD RELAY I F 6 B PR4 2 LCD RELAY I F 3 C PR4 2 LCD RELAY I F 6 B SIGNAL PAGE PAGE NAME LOCATION PR5 2 LCD RELAY I F 5 C PR5 2 LCD RELAY I F 6 B PVS 2 LCD RELAY I F 3 C PVS 2 LCD RELAY I F 6 B R...

Page 133: ... A27 27 A28 28 A29 29 A30 30 A31 31 C1 32 C2 33 C3 34 C4 35 C5 36 C6 37 C7 38 C8 39 C9 40 C10 41 C11 42 C12 43 C13 44 C14 45 C15 46 C16 47 C17 48 C18 49 B1 51 B2 52 B3 53 B4 54 B5 55 B6 56 B7 57 B8 58 B9 59 B10 60 B11 61 B12 62 B13 63 B14 64 B15 65 B16 66 B17 67 B18 68 B19 69 B20 70 B21 71 B22 72 B23 73 B24 74 B25 75 B26 76 B27 77 B28 78 B29 79 B30 80 B31 81 D1 82 D2 83 D3 84 D4 85 D5 86 D6 87 D7 ...

Page 134: ...UP 5700 ISA PWB SIGNAL PAGE PAGE NAME LOCATION 12V 1 ISA PWB 6 D VCC 1 ISA PWB 5 B VCC 1 ISA PWB 6 D VCC5 1 ISA PWB 1 B VCC5 1 ISA PWB 1 C 9 38 ...

Page 135: ...SUMI VLOW VHIGH 1 2 3 CN3 BHR 03VS 1 PGND 1 ICCFL 2 DIO 3 VC 4 AGND 5 NC 7 NC 8 SHDN 6 NC 9 NC 10 REF 11 VIN 12 VSW 16 BULB 15 BAT 14 ROYER 13 IC1 LT1184F R102 220K C103 1000pF R104 15 4KF 10 6 5 1 2 3 4 T1 841TN C1 2 2uF 16V C5 0 056uF 100V F1 ICP0 5 C2 2 2uF 16V R103 750 L1 56uH Q101 C5001 Q102 C5001 D101 SFPB54 D102 SFPB54 R101 100K R105 4 7K C104 1uF 16V 5 INVERTER PWB ...

Page 136: ...C B5 GND NC G5 G4 G3 NC B4 B3 B2 NC GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 31 CN2 CN31 Hsync GND R1 R3 R5 G0 G2 G4 GND B1 B3 B5 ENB VCC CK Vsync R0 R2 R4 GND G1 G3 G5 B0 B2 B4 GND VCC GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 CN1 CN30 Vsync CK ENB LINK LCD2 SCH 6 LCD RELAY PWB ...

Page 137: ...4 1 LCD RELAY PWB 8 C B5 1 LCD RELAY PWB 8 C G0 1 LCD RELAY PWB 8 C G1 1 LCD RELAY PWB 8 C G2 1 LCD RELAY PWB 8 C G3 1 LCD RELAY PWB 8 C G4 1 LCD RELAY PWB 8 C G5 1 LCD RELAY PWB 8 C R0 1 LCD RELAY PWB 8 C R1 1 LCD RELAY PWB 8 C R2 1 LCD RELAY PWB 8 C R3 1 LCD RELAY PWB 8 C R4 1 LCD RELAY PWB 8 C R5 1 LCD RELAY PWB 8 C HYSNC 1 LCD RELAY PWB 8 C VSYNC 1 LCD RELAY PWB 8 C CK 1 LCD RELAY PWB 8 C 9 41...

Page 138: ... 1 2W 24K 1 2W 12V R34 8 2K R39 22 R35 2 7K 1 2 4 3 PC2 TLP721F TLP621 R40 16K C29 1µF 50V PR D9 HZM5 1B1 RD5 1SB1 DTZ5 1A 5V R38 1K Q4 DTC114EUA RN1302 Q5 DTC114EUA RN1302 4 2 8 11 12 T1 P1165 7 13 14 6 9 10 D16 FMB26L D10 SF10SC4 Q3 2SK2512 K2312 R37 1K R20 10K 8 1 2 3 4 5 6 7 IC1 SR101 R36 56 C20 330µF 35V PW PY LXJ D15 1SS270A 3 2 1 IC3 C21 100µF 35V PW PY C30 C31 C32 C33 2200µF 10V PW PY x 4 ...

Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...

Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...

Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...

Page 142: ...5 UP 5700 INVERTER PWB A side UP 5700 ISA PWB B side UP 5700 INVERTER PWB B side 4 UP 5700 ISA PWB A side 10 4 ...

Page 143: ...Apply silicone bond 3490 on the board surface and attach RA4 120 ohm 1 4W between pins 1 3 of IC4 Apply silicone bond 3490 on the board surface Put V2 tube on R43 1k ohm 1 4W and attach to the plus side of pin 1 and C23 of IC4 1 2 A 1mm wide pattern is cut in position X 3 2 6 UP 5700 LCD RELAY PWB A side CN2 30 2 31 1 UP 5700 LCD RELAY PWB B side 10 5 ...

Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...

Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...

Page 146: ...stored in a retrieval system or transmitted In any form or by any means electronic mechanical photocopying recording or otherwise without prior written permission of the publisher SHARP CORPORATION Information Systems Group Quality Reliability Control Center Yamatokoriyama Nara 639 11 Japan 1997 December Printed in Japan ...