Pin
Name
Features
Features other than port
P50/R
´
D,
P51/T
´
D,
P52/SCLK,
P53/S R D Y
I/O port P5
4-bit I/O port with almost the same feature as P0.
CMOS input level is used, and the form of output
is CMOS 3-state.
Serial I/O pin
P60/INT5/
OBF2
I/O port P6
2-bit I/O port with almost the same feature as P0.
CMOS input level is used, and the form of output
is CMOS 3-state.
Interrupt input pin
Data bus buffering pin
P61/CNTR0
Timer X pin
A0,
S,
E/R,
R/W/W
Input port
Control bus for the host CPU.
Input level can be switched between CMOS and TTL.
DQ0
~
DQ7
I/O port
8-bit data bus for the host CPU.
Input level can be switched between CMOS and TTL.
9-4. Functional block diagram
49
P0(8)
50 51 52 53 54 55 56
41
P1(8)
42 43 44 45 46 47 48
33
P2(8)
34 35 36 37 38 39 40
57
P3(8)
58 59 60 61 62 63 64
20
P4(8)
21 22 23 24 25 28 29
4
5
6
7
8
9 10 11
12
P5(4)
13 14 15
16 17 18 19
2
3
P6(2)
INT0
INT4
~
P0(8)
A
30
31
XIN
XOUT
32
VSS
27
RESET
1
VCC
26
CN VSS
RAM
ROM
CPU
X
Y
S
PCL
PS
PCH
CNTR0
INT5
W R S A0
Clock Input Clock Output
Reset Input
Data Bus
Clock Generator
Prescaler 12 (8)
Prescaler X (8)
Timer 1 (8)
Timer 2 (8)
Timer X (8)
System Bus
Interface
Comparator
Key-On-Wakeup
(n) I/O Port P6
I/O Port P5
I/O Port P4
I/O Port P3
I/O Port P2
I/O Port P1
I/O Port P0
DQ0~DQ7
5 – 28
Summary of Contents for UP-5700
Page 139: ...1 UP 5700 Main PWB CHAPTER 10 PWB LAYOUT A side 10 1 ...
Page 140: ...2 UP 5700 CPU PWB A side UP 5700 CPU PWB B side 10 2 ...
Page 141: ...3 UP 5700 KEY I F PWB A side CN2 UP 5700 KEY I F PWB B side 10 3 ...
Page 144: ...For components produced in January 1998 and onward Parts side Solder side 10 6 ...
Page 145: ...7 2 Sub PWB Side A Side B 10 7 ...
