UP-5900VS
CIRCUIT DESCRIPTION
5 – 9
BSEL[1:0]
I/O
These signals are used to select the system bus frequency. The frequency is determined by the processor(s), chipset,
and frequency synthesizer capabilities. All system bus agents must operate at the same frequency Individual proces-
sors will only operate at their specified front side bus (FSB) frequency. On motherboards which support operation at
either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will
select a 66 MHz system bus frequency.
These signals must be pulled up to 2.5V or 3.3 V with 1 K
Ω
resistor and provided as a frequency selection signal to the
clock driver/synthesizer.
note: BSEL1 is not used by the Celeron processor.
BR0#
I/O
The BR0# (Bus Request) pin drives the BREQ[0]# signal in the system. During power-up configuration, the central
agent asserts the BREQ0# bus signal in the system to assign the symmetric agent ID to the processor. The processor
samples it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s symmetric agent ID. The processor
asserts BR0# to request the system bus.
CPUPRES# (PPGA
and FC-PGA only)
O
The CPUPRES# signal provides the ability for a system board to detect the presence of a processor. This pin is a
ground on the processor indicating to the system that a processor is installed.
The CPUPRES# signal is defined to allow a system design to detect the presence of a terminator device or processor
in a PGA370 socket. Combined with the VID combination of VID[3:0]= 1111, a system can determine if a socket is
occupied, and whether a processor core is present.
PGA370 Socket Occupation Truth Table
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data path between the Intel Celeron
processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the Intel Celeron processor
system bus to indicate that the data bus is in use. The data bus is released after DBSY# is deasserted. This signal
must connect the appropriate pins on all Intel Celeron processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion.
Assertion of DEFER# is normally the responsibility of the addressed memory or I/O agent. This signal must connect the
appropriate pins of all Intel Celeron processor system bus agents.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating valid data on the data
bus. In a multicycle data transfer, DRDY# may be deasserted to insert idle clocks. This signal must connect the appro-
priate pins of all Intel Celeron processor system bus agents.
EDGCTRL
I
The EDGCTRL input provides AGTL+ edge control and should be pulled up to VCCCORE with a 51
Ω
m
5% resistor.
NOTE: This signal is NOT used on the FC-PGA package.
EMI
(S.E.P.P. only)
I
EMI pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0
Ω
) resistors. The
zero ohm resistors should be placed in close proximity to the Intel Celeron processor connector. The path to chassis
ground should be short in length and have a low impedance. These pins are used for EMI management purposes.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems
using MS-DOS*-type floating-point error reporting.
FLUSH#
I
When the FLUSH# input signal is asserted, the processor writes back all data in the Modified state from the internal
cache and invalidates all internal cache lines. At the completion of this operation, the processor issues a Flush
Acknowledge transaction.
The processor does not cache any new data while the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, the processor samples FLUSH# to determine its power-on configura-
tion.
HIT#, HITM#
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation results, and must connect
the appropriate pins of all Intel Celeron processor system bus agents. Any such agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM#
together.
IERR#
O
The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error. Assertion of IERR# is
usually accompanied by a SHUTDOWN transaction on the Intel Celeron processor system bus. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#.
IGNNE#
I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a numeric error and continue to
execute noncontrol floating-point instructions.
If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous
floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an I/O write instruction, it
must be valid along with the TRDY# assertion of the corresponding I/O Write bus transaction.
Signal
Type
Description
Signal
Value
Status
CPUPRES#
VID[3:0]
CPUPRES#
VID[3:0]
CPUPRES#
VID[3:0]
1
Any value
0
Anything other than '1111'
0
1111
PGA370 socket not occupied.
Processor core installed in the PGA370
socket.
Terminator device installed in the
PGA370 socket (i.e., no core present).
