UP-5900VS
CIRCUIT DESCRIPTION
5 – 23
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CPU INTERFACE SIGNALS
IRQ 12/M
I
INTERRUPT REQUEST 12. In addition to providing the standard interrupt function as described in the pin descrip-
tion for IRQ[3:7,9:11,14:15], this pin can also be programmed to provide the mouse interrupt function.
When the mouse interrupt function is selected, a low to high transition on this signal is latched by PIIX4E and an
INTR is generated to the CPU as IRQ12. An internal IRQ12 interrupt continues to be generated until a Reset or an I/
O read access to address 60h (falling edge of IOR#) is detected.
PIRQ[A:D]#
I/OD
PCI
PROGRAMMABLE INTERRUPT REQUEST. The PIRQx# signals are active low, level sensitive, shareable interrupt
inputs. They can be individually steered to ISA interrupts IRQ [3:7,9:12,14:15]. The USB controller uses PIRQD# as
its output signal.
SERIRQ/
GPI7
I/O
SERIAL INTERRUPT REQUEST. Serial interrupt input decoder, typically used in conjunction with the Distributed
DMA protocol.
If not using serial interrupts, this pin can be used as a general-purpose input.
Name
Type
Description
A20M#
OD
ADDRESS 20 MASK. PIIX4E asserts A20M# to the CPU based on combination of Port 92 Register, bit 1
(FAST_A20), and A20GATE input signal.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
CPURST
OD
CPU RESET. PIIX4E asserts CPURST to reset the CPU. PIIX4E asserts CPURST during power-up and when a
hard reset sequence is initiated through the RC register.
CPURST is driven inactive a minimum of 2 ms after PWROK is driven active.
CPURST is driven active for a minimum of 2 ms when initiated through the RC register. The inactive edge of
CPURST is driven synchronously to the rising edge of PCICLK. If a hard reset is initiated through the RC register,
PIIX4E resets its internal registers (in both core and suspend wells) to their default state.
This signal is active high for Pentium processor and active-low for Pentium II processor as determined by CONFIG1
signal.
For values During Reset, After Reset, and During POS, see the Suspend/Resume and Resume Control Signaling
section.
FERR#
I
NUMERIC COPROCESSOR ERROR. This pin functions as a FERR# signal supporting coprocessor errors. This
signal is tied to the coprocessor error signal on the CPU. If FERR# is asserted, PIIX4E generates an internal IRQ13
to its interrupt controller unit. PIIX4E then asserts the INT output to the CPU. FERR# is also used to gate the
IGNNE# signal to ensure that IGNNE# is not asserted to the CPU unless FERR# is active.
IGNNE#
OD
IGNORE NUMERIC EXCEPTION. This signal is connected to the ignore numeric exception pin on the CPU.
IGNNE# is only used if the PIIX4E coprocessor error reporting function is enabled. If FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h) causes the IGNNE# to be asserted.
IGNNE# remains asserted until FERR# is negated. If FERR# is not asserted when the Coprocessor Error Register
is written, the IGNNE# signal is not asserted.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
INIT
OD
INITIALIZATION. INIT is asserted in response to any one of the following conditions.
When the System Reset bit in the Reset Control Register is reset to 0 and the Reset CPU bit toggles from 0 to 1,
PIIX4E initiates a soft reset by asserting INIT. PIIX4E also asserts INIT if a Shut Down Special cycle is decoded on
the PCI Bus, if the RCIN# signal is asserted, or if a write occurs to Port 92h, bit 0. When asserted, INIT remains
asserted for approximately 64 PCI clocks before being negated.
This signal is active high for Pentium processor and active-low for Pentium II processor as determined by CONFIG1
signal.
Pentium Processor:
During Reset: Low
After Reset: Low
During POS: Low
Pentium II Processor:
During Reset: High
After Reset: High
During POS: High
INTR
OD
CPU INTERRUPT. INTR is driven by PIIX4E to signal the CPU that an interrupt request is pending and needs to be
serviced. It is asynchronous with respect to SYSCLK or PCICLK and is always an output. The interrupt controller
must be programmed following PCIRST# to ensure that INTR is at a known state.
During Reset: Low
After Reset: Low
During POS: Low
NMI
OD
NON-MASKABLE INTERRUPT. NMI is used to force a nonmaskable interrupt to the CPU. PIIX4E generates an
NMI when either SERR# or IOCHK# is asserted, depending on how the NMI Status and Control Register is pro-
grammed. The CPU detects an NMI when it detects a rising edge on NMI. After the NMI interrupt routine processes
the interrupt, the NMI status bits in the NMI Status and Control Register are cleared by software. The NMI interrupt
routine must read this register to determine the source of the interrupt. The NMI is reset by setting the corresponding
NMI source enable/disable bit in the NMI Status and Control Register. To enable NMI interrupts, the two NMI
enable/disable bits in the register must be set to 0, and the NMI mask bit in the NMI Enable/Disable and Real Time
Clock Address Register must be set to 0. Upon PCIRST#, this signal is driven low.
During Reset: Low
After Reset: Low
During POS: Low
SLP#
OD
SLEEP. This signal is output to the Pentium II processor in order to put it into Sleep state. For Pentium processor it
is a No Connect.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
Name
Type
Description
