PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 22 –
(2) PIN LAYOUT
(3) COMPACT FLASH MODE
(GENERAL-PURPOSE I/O TERMINAL)
Since the dedicated Compact Flash mode does not need address lines
PA11 - PA22 and CA11 - CA25, they can be used for other purposes.
However, it is difficult to use CA11 - CA25 because the card power sup-
ply might be turned off. PA11 -PA22 can easily used because LVDD is
fixed to 3.3V.
(3)-1. GPIO PINS (PA11 - PA19)
For this reason, pins PA11 to PA19 can be used as general-purpose I/
Os according to the setting in the CF mode.
(3)-2. GLUE-LOGIC PINS
[PA20, PA21: INPUT, PA22: OUTPUT]
The following logic (DFFx1) is connected to solve the problem with the
signal phase relationship between the panel controller and CPU
(SA1110).
Circuit diagram
GND
5O
110
CA23
5O
CA12
5O
CA24
5O
CA7
5O
CA25
5O
115
CA6
5O
CA5
HVDD
5O
CRESET
5O
CA4
5I
120
CWAIT_B
5O
CA3
5O
CA2
5O
CREG_B
5O
CA1
5I
125
CBVD2
5O
CA0
5I
CBVD1
HVDD
5IO
CD0
5IO
130
CD8
5IO
CD1
5IO
CD9
5IO
CD2
5IO
CD10
5I
135
CIOIS16_B
GND
LVDD
3I
CCD1_B
3I
CCD2_B
3I S
140
CVS1_B
3I S
CVS2_B
3O CVCCDOWN_B
3O
143
CVCC3EN_B
3O
CVCC5EN_B
3I
TEST
3I
71
RESET_B
3I
70
PCE1_B
3O
IOIS16_B
3I
PREG_B
3I
PCE2_B
3O
PWAIT_B
3I
65
POE_B
3I
PIOR_B
LVDD
3I
PWE_B
3I
PIOW_B
3I
60
CS4_B
3I
OE_B
3I
WE_B
3O
PIRQ_B
3O
PRDY
3I
55
PSKTSEL
3I
PSKTSEL2
GND
3I
PA0
3I
PA1
3I
50
PA2
3I
PA3
3I
PA4
3I
PA5
3I
PA6
3I
45
PA7
LVDD
3I
PA8
3I
PA9
3I
PA10
3I S
40
PA11
3I S
PA12
3I S
38
PA13
GND
GND
74
CD3
5IO
75
CD4
5IO
CD11
5IO
CD5
5IO
CD12
5IO
CD6
5IO
80
HVDD
CD13
5IO
CD7
5IO
CD14
5IO
CCE1_B
5O
85
CD15
5IO
CA10
5O
CCE2_B
5O
COE_B
5O
CA11
5O
90
GND
CIORD_
B
5O
CA9
5O
CIO
WR_B
5O
CA8
5O
95
CA17
5O
CA13
5O
CA18
5O
CA14
5O
CA19
5O
100
HVDD
CWE_B
5O
CA20
5O
CRD
Y
5I
CA21
5O
CA16
5O
CA22
5O
107
CA15
5O
GND
P
A14
3I S
Buffer type
35
P
A15
3I S
P
A16
3I S
P
A17
3I S
P
A18
3I S
P
A19
3I S
30
LVDD
P
A20
3I
P
A21
3I
P
A22
3IO
P
A23
3I
25
P
A24
3I
P
A25
3I
LVDD
PD15
3IO
PD7
3IO
20
PD14
3IO
PD6
3IO
PD13
3IO
PD5
3IO
PD12
3IO
15
GND
PD4
3IO
PD11
3IO
PD3
3IO
PD10
3IO
10
PD2
3IO
PD9
3IO
PD1
3IO
PD8
3IO
PD0
3IO
LVDD
VA
C
T
3I
CREV
3I
2
CVPP5EN_
B
3O
CVPP3EN_
B
3O
Scoop ASIC
TQFP144pins (126 user pins and 18 power supply pins)
Buffer with pull-up/pull-down resistance control function
I=Input buffer, O= Output buffer, IO=I/O buffer
VDD (3=3.3V fixed [LVDD], 5=5/3.3/0V variable [HVDD]
The shaded items show card pins which
require an external pull-up resistance.
Pin arrangement used when
CREV pin is fixed to Lo.
VDD=3.3V (fixed power supply)
HVDD=5.0/3.3/0V (Variable)
Buffer type
Example: 3IS(Special)
Note:
1. In the CF mode, the above address bus pins are automati-
cally pulled down if set to the GPIO input mode (initial
value). The pull-down resistance value is 40k-240k
Ω
(TYP100k
Ω
)
2. These pins are basically used for address bus input, and
thus input is not Schmitt received.
L-LCLK
L-PCLK
PA20
PA21
SA1110 (CPU)
RESET_B
DFF
PA22
HS_OUT
HS
Scoop (CF card mode.)
Panel controller