PC-UM10M
SL-5500 HARDWARE DESCRIPTION
– 23 –
2-8. DAC (M62332)
(1) PIN CONNECTION DIAGRAM
(2) BLOCK DIAGRAM
(3) PIN DESCRIPTION
2-9. DAC (PCM1741)
(1) BLOCK DIAGRAM
(2) PIN CONFIGURATION
(3) PIN ASSIGNMENTS
Pin No.
Symbol
Functional description
6
SDA
Serial data input pin
7
SCL
Serial clock signal input pin
1
AO1
8-bit resolution D/A converter output pin
(After power is turned on, all channels are
reset and DAC data 00h is outputted.)
2
AO2
8
VCC
Power supply voltage pin
5
GND
GND pin
M62332FP
1
AO1
2
AO2
3
N.C.
4
N.C.
8
VCC
7
SCL
6
SDA
5
GND
8
7
6
5
1
2
3
4
VCC
SCL
SDA
GND
AO1
AO2
N.C.
N.C.
I C BUS TRANSCEIVER
2
Power-on
reset
Channel
decoder
8-bit latch
8-bit latch
8-bit upper
segment R-2R
8-bit upper
segment R-2R
BCK
LRCK
DATA
ML
MC
MDI
SCK
System
Clock
Manager
System Clock
Audio
Serial
Port
Serial
Control
Port
8x
Over-
sampling
Digital
Filler
with
Function
Controller
Enhanced
Multi-level
Delta-
Slgma
Modulator
Zero Detect
Power Supply
Output Amp
and Low-pass
Filter
DAC
DAC
Output Amp
and Low-pass
Filter
VOUTL
VCOM
VOUTR
ZEROL
ZEROR
VD
D
DGND
VC
C
AGND
PIN
NAME
TYPE
DESCRIPTIONS
1
BCK
IN
Audio data bit clock input.
*1
2
DATA
IN
Audio data digital input.
*1
3
LRCK
IN
L-channel and R-channel Audio
data latch enable input.
4
DGND
Digital ground.
5
VDD
Digital power supply, +3.3V.
6
VCC
Analog power supply, +3.3V
7
VOUTL
OUT
Analog output for L-channel.
8
VOUTR
OUT
Analog output for R-channel.
9
AGND
Analog ground.
10
VCOM
Common voltage decoupling.
11
ZEROR/ZEROA
OUT
Zero flag output for R-channel/
Zero flag output for L/R-channel.
12
ZEROL/NA
OUT
Zero flag output for
L-channel/No assign.
13
MD
IN
Mode control data Input.
*2
14
MC
IN
Mode control clock input.
*2
15
ML
IN
Mode control latch input.
*2
16
SCK
IN
System clock input.
Note:
*1
Schmitt trigger input, 5V tolerant.
*2
Schmitt trigger input with internal pull-down, 5V tolerant.
1
BCK
2
DATA
3
LRCK
4
DGND
5
VDD
6
VCC
7
VOUTL
8
VOUTR
16
15
14
13
12
11
10
9
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
VCOM
AGND
PCM1741