- 60 -
When CPU speed set to 100MHz, DRAM speed can be set to
100MHz( by Host Clock) , or 133MHz (by Host Clock+33MHz).
When CPU speed set to 133MHz, DRAM speed only set to 133MHz
(by Host Clock).
DRAM Timing
This item allows you to select the value in this field, depending on
whether the board using which kind of DDR DRAM.
Ø
The Choice: Manual or By SPD.
SDRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of
CAS latency depends on the DRAM timing. Do not reset this field from
the default value specified by the system designer.
Ø
The Choice: 3, 2.5 or 2
Bank Interleave
The interleave number of internal banks, can be set to 2 way, 4 way
interleave or disabled. For VCM and 16Mb type dram chips, the bank
interleave is fixed at 2 way interleave.
When the dram timing is selected by SPD, it will be set by the value on
SPD of the RAM module(SDR).
Ø
The Choice: Disabled, 2 Bank, or 4 Bank.
Precharge to Active (Trp)
This item allows you to Precharge Command to Active Command
Period.
Ø
The Choice: 2T or 3T.
Active to Precharge (Tras)
This item allows you to Active Command to Precharge Command
Period.
Ø
The Choice: 5T or 6T.
Active to CMD (Trcd)
This item allows you to Active to CMD.
Ø
The Choice: 2T or 3T.
DRAM Burst Len
This item allows you to select Dram Burst Length.
Ø
The Choice: 4 or 8.
