Systemsoftware
2-22
System- and communication configuring D7-SYS - SIMADYN D
Edition 03.2001
When service makes changes such as these, there are only a limited
number of reserves for additional interconnections. The number of
additional interconnections is
•
minimum of 10 additional interconnections, and
•
maximum of 20 % of the already configured number of
interconnections.
There are already 5 interconnections from cyclic task T2 to cyclic task T3.
For interconnection changes from T2 to T3 there is then a reserve of 10
interconnection changes, as 20 % of 5 = 1, however a minimum of 10.
For 100 existing interconnections, there are an additional 20 reserve
interconnections, as 20 % of 100 = 20.
A differentiation is made between interconnections within a task, between
tasks of a CPU and between several CPUs of a station. For operation
with several CPUs, an additional differentiation is made between
standard- and fast $ signals.
For interconnections between tasks of a CPU, the alternating buffer
system on the processor is used. The maximum number of
interconnections is limited by the main memory expansion stage.
Connections between several CPUs of a station are handled via the
communication buffer modules. The number of possible interconnections
is dependent on the communication buffer module used and the signal
types.
Further information
on the communication buffer modules refer to the " SIMATIC
TDC/SIMADYN D hardware" Manual
For an MM11 module with 64 Kbyte memory each for the L- and C bus,
the following are obtained when using:
Signal type
Bytes/interconnection
Number of interconnections
Fast $ signals
4
Approx. 16000 per bus type
Standard signal
Max. 36
(No. CPUs + 1)* 4)
Min. 1800 per bus type
Table 2-9
Calculating the maximum number of interconnections
NOTE
If standard and fast interconnections are combined, an appropriately
lower number are obtained.
Example:
Limited number of
interconnections
