Systemsoftware
System- and communication configuring D7-SYS - SIMADYN D
2-25
Edition 03.2001
2.1.7.2 Process image for cyclic tasks
For input blocks, which have a system component or whose system
component is activated, the input signals are read-in from the hardware
and buffered. The signals are evaluated with the blocks in the standard
mode of the same cycle.
Read-in
the hard-
ware
Process value(s)
und result at the
block outputs
Value(s) in
the buffer
memory
Value(s) from
the buffer
memory
Sampling time TA(n)
Sampling time TA (n+1)
System mode
Normal mode
Fig. 2-7
Sequence of the system mode for input blocks
For output blocks, which have a system component and whose system
component is activated, in the standard mode of the previous cycle, the
signals to be output are calculated corresponding to the block function
and the actual connection (I/O) values. These signals are buffered.
Signals are output to the hardware in the system mode at the start of the
next sampling cycle.
Input blocks with
system component
Output blocks with
system component
