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325
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
2.3.10.6
I²C
The ERTEC 200P contains one I
2
C module for general purpose applications (I
2
C_3,
master / slave interface). This module is located at the Toplevel and controlled by the
ARM926EJ-S. Another I
2
C module (master / slave interface) is located in the PN-IP. The
two I
2
C interfaces for the LWL Tranceiver (I
2
C_1/2) and the general purpose interface
(I
2
C_3) are multiplexed with other peripheral functions on the GPIO interface.
In the document 'I2C_Philips.pdf' /29/ (see chapter 7.2) you will find the I
2
C Bus Specifi-
cation and in the document 'mi2c_ps.pdf' the discription of the used Inventra IP MI2C /
30/:
To use the direct access to the I
2
C bus, the ARM must access appropriately the I
2
C inter-
face macro registers. These registers are contained in the I
2
C interface address area.
The complete functional description of the I
2
C interface macro and the included registers
is contained in the MI2C document.
The I
2
C interface contains 2 registers (SW_I2C_EN and SW_I2C_CTRL) which allow to
control the I
2
C-Bus signals by Software. This software interface is enabled by setting bit 0
in register SW_I
2
C_EN. If this software interface is enabled, the rest of the I
2
C interface
cannot be used.
The 8Bit I
2
C modules are connected to the APB / SC-Bus (PN-IP). Only word addresses
are used for addressing the internal registers. In the case of a write to the module the bit
position 31-8 are ignored and in the case of a read from the modul these bit positions are
driven with '0'.
2.3.10.6.1 Baudrate generator
In contrast to the MI2C IP specification, the
C
lock
C
ontrol
R
egister (MI2C_CCR) in the
I
2
C interface cannot be written because the register is not implemented. The Clock Con-
trol Register for the general purpose I
2
C interface (I
2
C_3) is contained in the SCRB
(CCR_I2C). This allows the SCL clock pulse frequency on the I
2
C bus to be set (see
chapter 2.3.10.9.22, System-Control-Register-Block (SCRB).
For a baudrate of 100 kBaud on the I
2
C bus the module requires an internal enable signal
of 1 MHz. Therefore the input clock has to be divided. This will be done by configuring the
register CCR_I2C in the SCRB module. The register CCR_I2C is not configured after
reset.
Formula for calculating the divider value:
((PCLK MHz) / (C 1)) = 1 MHz
Example:
If
PCLK = 125 MHz
then
CCR_I2C = 124d = ("01111100b")
Restrictions
Only the baudrate of 100 kBaud (normal mode) is supported. The baudrate of 400 kBaud
(fast mode) cannot be supported because a divider value to generate 4MHz is not config-
urable in CCR_I2C by 125MHz (PCLK).
2.3.10.6.2 IO Expansion Unit
The "IO Expansion Unit" is used to operate a maximum of 4 commonly usable 8-bit IO
expanders connected to the I
2
C interface of the ERTEC 200P. The corresponding regis-
ters are located in the I
2
C address area.