Copyright © Siemens AG 2016. All rights reserved
368
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
The vector address for the secondary boot loader following an ARM926EJ-S SW reset is
saved in RES_SOFT_RETURN_ADDR.
2.3.10.9.5
ACCESS_ERROR and QVZ Register
Access errors by the individual modules are combined here (OR logic operation) and
forwarded to the interrupt controller (ARM-ICU) as AHB_Address_Error (IRQ51),
APB_Address_Error (IRQ52), EMC_Address_Error (IRQ53) or IP_Address_Error
(IRQ86):
1. Master access error interrupt (AHB_Address_Error): QVZ error at
ML-AHB
caused
by master access by ARM_I, ARM_D, PN, GDMA and HostIF.
2. Slave access error interrupt (APB_Address_Error): QVZ error at
APB
caused by
master access by ARM_I, ARM_D, PN, GDMA and HostIF.
3. EMC access error interrupt (EMC_Address_Error): QVZ error at
EMC
caused by
master access by ARM_I, ARM_D, PN, GDMA, HostIF.
4. Slave access error interrupt (IP_Address_Error): Slave module
access error
at
the APB or AHB bus (PN-IP, PerIF, I-filter, HostIF, SCRB).
The QVZ_AHB_M contains all the modules (AHB masters) that have caused an access
error. Following an activated interrupt, the CPU can read the QVZ_AHB_M register and
indentify the trigger module on the basis of the bit position in the register. The software
can then read the QVZ registers of the AHB masters in the SCRB (QVZ_AHB_ADR;
QVZ_APB_ADR; QVZ_AHB_CTRL) and identify the address and access type that led to
the error.
As a general rule, an access error sets the corresponding bit in QVZ_AHB_M, freezes the
corresponding address and control information and generates an interrupt.
Until the bit of an AHB master in QVZ_AHB_M is deleted by the SW, another AHB
access error (from any AHB master) will
not
be saved. This allows unique assignment
of the address and control information in the QVZ_AHB_ADR, QVZ_APB_ADR and
QVZ_AHB_CTRL registers to the corresponding AHB master, even when multiple ac-
cess errors from different AHB masters occur at the same time.
Until the bit of an AHB/APB slave MODUL_ACCESS_ERR is cleared by the SW,
another access error for the same APB slave will
not
be saved. An access error for
another APB slave can however be locked at the same time, as the address and con-
trol information for the erroneous access is buffered in the corresponding APB module
or in the SCRB register (ACCESS_ERROR_SCRB) and locked.
2.3.10.9.6 PLL Status Register
You can read the status of the PLL LOCK bit and the oscillator loss information by read-
ing the PLL status register.
2.3.10.9.7 Memory Swapping
The reset vector of the ARM926 processor points to address 0x0000_0000. That is why
the mirrored area of the boot ROM starts at address 0x0000_0000 (
MEM_SWAP
= "00")
