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2.1.9 Debug and Trace Interface

The ETM macro cell of the ARM946E-S can be used as a debug and trace interface in the ERTEC 200. With this
interface, the user software running on the ARM946E-S and the user data can be analyzed and traced. The ETM
module is a standard module recommended by ARM on which various available debuggers can be run. If the trace
interface is used, the LBU interface is not available (configuration setting "Trace On“, see Section 2.1.2). If the trace
interface is used, the required parameter assignment of the ETM macro cell must be performed with the debugger, so
that the required pins are switched to trace functionality.
The ETM macro cell is described in documents /9/ and /10/.

2.1.10 Serial Asynchronous Interfaces

The EB 200 has an RS232 interface with a 9-pin SUB-D male connector, which is designated X7. Only the RxD and
TxD signals are lead through. The interface can be deactivated using jumper X11 11/12 (SYS_CONFIG[2]) (see also
Section 2.1.2 ).

2.1.11 General Purpose Interface (GPIO)

The GPIO interface of the ERTEC 200 consists of 45 I/O that can be divided into two groups. The GPIOs[31:0] are
multiplexed with various alternative function blocks by means of the APB bus. GPIO [31,30,1,0] can be used as inputs
with interrupt capability. Alternatively, the GPIOs[44:32] can be selected for the LBU interface using the configuration
setting (see Section 2.1.2).

Signal
Name
Function 1

Alternative
Function 2

Alternative
Function 3

Alternative
Function 4

Use (Default)

GPIO0

P1-DUPLEX_N-
LED

GPIO

(interrupt-capable)

GPIO1

P2-DUPLEX_N-
LED

GPIO

(interrupt-capable)

GPIO2

P1-SPEED_N-
100LED (TX/FX)

Bus error - LED

GPIO3

P2-SPEED_N-
100LED (TX/FX)

Sync

error

-

LED

GPIO4

P1-LINK_N-LED

Link Port1 LED

GPIO5

P2-LINK_N-LED

Link Port2 LED

GPIO6

P1-RX_N-LED

P1-TX_N-LED P1-ACTIVE_N

-LED

Activity Port1 LED

GPIO7

P2-RX_N-LED

P2-TX_N-LED P2-ACTIVE_N

-LED

Activity Port2 LED

GPIO8 UART_TXD

UART (Transmit Data, O)

GPIO9 UART_RXD

UART (Receive Data, I)

GPIO10 UART_DCD_N

GPIO

GPIO11 UART_DSR_N

GPIO

GPIO12

UART_CTS_N

GPIO

GPIO13

IRTE_TRIG_
TRACE_UNIT

GPIO

GPIO14 DBGACK

GPIO

GPIO15 WD_WDOUT0_N

GPIO

GPIO16 SPI1_SSPCTLOE

GPIO

GPIO17

SPI1_SSPOE

GPIO

GPIO18

SPI1_SSPRXD

SPI1 (Receive Data; I)

GPIO19

SPI1_SSPTXD

SPI1 (Transmit Data; O)

GPIO20

SPI1_SCLKOUT

SPI1 (ClkOut Master; O)

Copyright © Siemens AG 2010. All rights reserved.

16

EB 200 Manual

Technical data subject to change

Version 1.1.4

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Summary of Contents for ERTEC EB 200

Page 1: ...EB 200 Copyright Siemens AG 2010 All rights reserved Page 1 EB200 Manual Technical data subject to change Version 1 1 4 Evaluation Board ERTEC 200 Manual ...

Page 2: ...eviewed regularly Necessary corrections are included in subsequent editions Suggestions for improvement are welcomed Copyright Siemens AG 2010 All rights reserved The reproduction transmission or use of this document or its contents is not permitted without express written authority Offenders will be liable for damages All rights including rights created by patent grant or registration of a utilit...

Page 3: ...sts e g debugging terminal outputs etc Structure of this Manual This manual describes the ERTEC 200 evaluation board The manual is structured as follows o Section 1 Introduction o Section 2 Hardware Structure of the EB 200 o Section 3 Memory Distribution of the EB 200 o Section 4 Operating Modes of the EB 200 o Section 5 JTAG Interface of the EB 200 o Section 6 Settings of the EB 200 o Section 7 C...

Page 4: ...ntative Please send your written questions comments and suggestions regarding the manual to the hotline via the e mail address indicated above In addition you can receive general information current product information FAQs and downloads pertaining to your application on the Internet at http www siemens com comdec Technical Contacts for Germany Worldwide Siemens AG Automation Drives ComDeC Phone 0...

Page 5: ...CI Reset 21 2 4 3 Watchdog and Software Reset 21 2 5 Clock System of the EB 200 21 2 5 1 Clock Pulse Supply of PCI Interface 21 2 5 2 Clock Pulse Supply of EB 200 via a Quartz Crystal 21 2 5 3 Clock Pulse Supply of EB 200 via an Oscillator 21 2 5 4 Cycle for F Timer 21 2 6 Ethernet Interface of the EB 200 22 3 Memory Allocation of EB 200 23 3 1 Memory Mapping 23 3 2 Detailed Memory Description 24 ...

Page 6: ...figuration Connector X10 40 8 2 System Configuration Connector X11 41 9 Structure of the EB 200 42 9 1 Mechanical Structure 42 9 2 Front and Display Element 42 10 Miscellaneous 44 10 1 Acronyms Glossary 44 10 2 References 45 Copyright Siemens AG 2010 All rights reserved 6 EB 200 Manual Technical data subject to change Version 1 1 4 ...

Page 7: ...terface 31 Table 13 Pin Assignment for LBU Interface 33 Table 14 Pin Assignment for External DC Supply 33 Table 15 Pin Assignment for Ethernet Switch Interface Downlink 34 Table 16 Pin Assignment for UART 34 Table 17 Pin Assignment for GPIO 15 to 0 35 Table 18 Pin Assignment for GPIO 31 to 16 35 Table 19 Pin Assignment for GPIO 44 to 32 36 Table 20 Pin Assignment for X30 EMIF Address Bits 36 Table...

Page 8: ...onfiguration for a PROFINET IO device no changes or only minor changes have to be made in the board support package BSP for your additionally required hardware The board support package adapts the operating system to the hardware see 3 Procedure You can use ERTEC 200 to develop your own hardware in one of two ways o By using a test board on the EB 200 to adapt and test your application circuit o B...

Page 9: ...llowing elements are available on the EB 200 PC front panel element with o 2 RJ45 sockets with integrated magnetics o 2 LEDs Link and Activity per RJ45 socket Optional LED display Speed and Duplex o 2 LEDs for additional status indicators o External DC power supply in stand alone mode Flash memory 4 Mbytes Flash memory 512 Kbytes socketed PLCC32 SDRAM 64 Mbytes SRAM 8 Mbytes SPI Data Flash and EPR...

Page 10: ...tor for direct LBU Master Interface MII Diagnostics SRAM 2x4MB 32Bit Figure 1 Block Diagram of the EB 200 Note On the evaluation board EB200 hardware release ES35 and newer that is included in the development kit V3 2 0 and newer the following components are no more used and no more assembled NAND Flash SMSC LAN91C111 Ethernet Chip RJ45 female connector The boards are fully compatible to the prior...

Page 11: ... T M G P IO 1 x U A R T S P I1 In te rfa ce 3 x T im e r W a tch d o g F T im e r ARM9 clock 50MHz 100MHz 1 1 2 5 M H z S C B u s 5 0 M H z 3 2 B it 2 P o rt S w itc h S w itch C o n tro l K S R A M 6 4 k B yte E th e rn e t K a n a l P o rt 0 E th e rn e t K a n a l P o rt 1 2 1 2 0 3 2 5 G P IO U A R T S P I T im e r W a tc h d o g P H Y 0 A H B W ra p p e r S la v e M a s te r Slave Slave 2 Sla...

Page 12: ...MII Off ETM9 On 1 1 1 LBU Off GPIO44 32 On int PHYs Off ext MII On ETM9 Off 0 0 ARM clock 50 MHz 0 1 ARM clock 100 MHz 1 0 ARM clock 150 MHz 1 1 Reserved LBU mode CONFIG 2 0 The LBU interface is active for access of a host processor system to internal components of the ERTEC 200 The internal PHYs are used in this operating mode Debugging of internal PHYs and diagnostics via the trace interface are...

Page 13: ... boot modes on the EB 200 can be set by means of jumpers X10 1 2 to X10 7 8 Additional jumper settings on connector X11 5 6 are necessary in SPI boot mode These jumpers are described in Sections 8 1 and 8 2 The following download modes are supported BOOT 3 X10 7 8 BOOT 2 X10 5 6 BOOT 1 X10 3 4 BOOT 0 X10 1 2 BOOTING OF 0 0 0 0 External ROM with 8 bit data width 0 0 0 1 External ROM with 16 bit dat...

Page 14: ...witch provides the required function for PROFINET IO It contains the following functions Configuration register for IRT switch 64 Kbytes of K RAM for RT and IRT communication The IRT switch functions are described in document 3 2 1 7 Interrupt System of the EB 200 The EB 200 has two interrupt controller units that can only be operated by the ARM946E S IRQ controller unit with 16 inputs for low pri...

Page 15: ...n chip select signal CS_PER0_N The socketed boot Flash is addressed with CS_PER0_N by means of boot jumper J2 External ROM 8 bit data width see Section 8 The 4 Mbyte firmware Flash is then selected with CS_PER1_N If the EB 200 is operated with a debugger ICE the boot Flash can be omitted as the firmware Flash can be programmed directly The following blocks of the EB 200 can be selected with the ch...

Page 16: ...d into two groups The GPIOs 31 0 are multiplexed with various alternative function blocks by means of the APB bus GPIO 31 30 1 0 can be used as inputs with interrupt capability Alternatively the GPIOs 44 32 can be selected for the LBU interface using the configuration setting see Section 2 1 2 Signal Name Function 1 Alternative Function 2 Alternative Function 3 Alternative Function 4 Use Default G...

Page 17: ... The GPIO is used as chip select for SPI Data Flash or SPI EEPROM if SPI Bootmode is selected setting see Table 2 GPIO23 SPI_SCLKIN IRTE_TRIG_ TRACE_UNIT IRT SYNC Direction O RS485 GPIO24 PLL_EXT_IN_N IRT SYNC Input GPIO25 TGEN_OUT1_N IRT SYNC Output GPIO26 TGEN_OUT2_N GPIO GPIO27 TGEN_OUT3_N GPIO GPIO28 TGEN_OUT4_N GPIO GPIO29 TGEN_OUT5_N CPLD TDO Input GPIO30 TGEN_OUT6_N ETH INT Ethernet Interru...

Page 18: ...Resourcen LBU_D15 GPIO41 GPIO41 B B B GPIO I up LBU or GPIO LBU_RDY_N GPIO42 GPIO42 O B B GPIO I up LBU or GPIO LBU Mode LBU Ready signal Polarity dependent on input pin LBU_POL_RDY Output driver always enabled LBU_IRQ0_N GPIO43 GPIO43 O B B GPIO I up LBU or GPIO LBU Mode Low active interrupt No open drain LBU_IRQ1_N GPIO44 GPIO44 O B B GPIO I up LBU or GPIO LBU Mode Low active interrupt No open d...

Page 19: ...ired to load firmware 2 Boot user Flash AMD type AMD29DL323GB 90EI T 4 Mbyte memory capacity 16 bit data width Programming performed with JTAG Intended for applications that work directly from the Flash 2 2 4 Serial Flash EEPROM The ERTEC 200 supports the following types in Boot from SPI boot mode Serial data Flash 128 Kbytes ATMEL type AT45DB011 Serial EEPROM 64 Kbytes ATMEL type AT25HP512 The fo...

Page 20: ...ES_N is activated Discrete PHYs are reset Output SRST_N is activated Debug logic is reset Output RESET_N is wired to I O slot Host Reset If the EB 200 is operated with an active host the connected host reset acts the same as the RESET_N signal The effects of the host reset are the same as for the power on reset Resetting the Debug Interface The debug interface is linked to the two reset signals SR...

Page 21: ...00 via the ERTEC 200 pins CLKP_A and CLKP_B 2 5 3 Clock Pulse Supply of EB 200 via an Oscillator Optionally the EB 200 can also be supplied with an oscillator clock pulse In this case the 25 MHz clock pulse is feed at the ERTEC 200 pin CLKP_A In both cases the available 25 MHz clock pulse generated in the ERTEC 200 via the clock pulse output REF_CLK can be used by external PHYs The following clock...

Page 22: ...tocrossover Autopolarity Link and Activity LED functionality After reset of the EB 200 the PHYs are inactive and must first be activated via the software The PHYs are connected to two RJ45 Ethernet sockets via a transformer Two LEDs for Link and Activity displays are integrated for each RJ45 socket Copyright Siemens AG 2010 All rights reserved 22 EB 200 Manual Technical data subject to change Vers...

Page 23: ...RAM 0 128 MB EMIF memory 0 64 MB Boot ROM 0 8 KB EMIF SDRAM 0 128 MB EMIF memory 0 64 MB Boot ROM 0 8 KB EMIF SDRAM 0 128 MB EMIF memory 0 64 MB 1000 0000 1FFF FFFF 1 IRT switch controller IRT switch controller IRT switch controller Not used 2000 0000 2FFF FFFF 2 EMIF SDRAM EMIF SDRAM EMIF SDRAM EMIF SDRAM 3000 0000 3FFF FFFF 3 EMIF Area Bank 0 3 EMIF Area Bank 0 3 EMIF Area Bank 0 3 EMIF Area Ban...

Page 24: ...FFFF After reset Boot ROM 8 Kbytes physical Memory swap 00b After memory swap EMIFSDRAM 128 Mbytes physical Memory swap 01b or EMIF memory 64 Mbytes physical Memory swap 10b From ARM9 perspective the locked I cache 2 4 6 Kbytes or a D TCM 4 Kbytes can be displayed 1 IRT switch 256 Mbytes 1000_0000 1FFF_FFFF 2 Mbytes physical 2 7 mirrored 0 1 MBytes for IRT register 1 2 MBytes for KRAM 2 EMIF SDRAM...

Page 25: ... 4000_2700 4000_27FF 8 bytes physical Not used 4000_2800 4000_FFFF Not used 4001_0000 4FFF_FFFF 5 ARM ICU 256 Mbytes 5000_0000 5FFF_FFFF ARM Interrupt controller 128 bytes physical 6 Not used 256 Mbytes 6000_0000 6FFF_FFFF 7 EMIF register 256 Mbytes 7000_0000 7FFF_FFFF Control register for external memory interface 64 bytes physical 8 DMA register 256 Mbytes 8000_0000 FFFF_FFFF DMA controller 16 b...

Page 26: ...ecognizes this with an entered Flash image The boot software then branches immediately to the user software contained in the Flash Debugging is then possible using the serial RS232 interface or the debug Ethernet port 4 3 Operating the EB 200 with LBU Mode If the EB 200 is operated in LBU mode the user must take the following precautions Provision of a HW reset from the host Provision of the 5 V v...

Page 27: ... X11 The ETM9 module must be enabled CONFIG 6 5 2 101 b see Section 2 1 2 Pin EN_TRACE_GPIO_N High with SYS_CONFIG 1 0 01 b see Section 2 1 2 This separates the trace port from the remaining logic by means of bus switches D4 and D5 The following companies have debuggers and trace modules for the ARM946E in their program Lauterbach JTAG Debugger Power Trace for ARM9 Hitex Tanto for ARM Tanto Trace ...

Page 28: ...M Bank Config 0x7000_0008 0x0000_0521 9CAS 13RAS 2CAS Delay SDRAM Refresh Control 0x7000_000C 0x0000_0320 Refresh every 8 us ASYNC Bank0 Config 0x7000_0010 0x0462_2311 16 bit 120 ns RD WR 20 ns setup hold ASYNC Bank1 Config 0x7000_0014 0x0462_2311 16 bit 120 ns RD WR 20 ns setup hold ASYNC Bank2 Config 0x7000_0018 0x0462_2312 32 bit 120 ns RD WR 20 ns setup hold ASYNC Bank3 Config 0x7000_001C 0x04...

Page 29: ...o 16 X21 2x10 pin plug connector o GPIO 44 to 32 X22 2x8 pin plug connector o I O bus X30 32 each with 2x13 pin plug connector o Trace connector for ETM of ARM946E S X60 38 pin Mictor connector o JTAG connectors for ICE or debugger X61 2x10 pin plug connector o Reserved X62 2x5 pin plug connector o Reserved X63 1x8 pin plug connector The following figure is a schematic representation of the connec...

Page 30: ...Address data B23 AD 27 Address data A23 AD 26 Address data B24 AD 25 Address data A24 M Ground B25 3 3 V Supply A25 AD 24 Address data B26 CBE_N 3 Command byte enable A26 IDSEL CS for Config B27 AD 23 Address data A27 3 3 V Supply B28 M Ground A28 AD 22 Address data B29 AD 21 Address data A29 AD 20 Address data B30 AD 19 Address data A30 M Ground B31 3 3 V Supply A31 AD 18 Address data B32 AD 17 A...

Page 31: ...nd B57 M Ground A57 AD 02 Address data B58 AD 01 Address data A58 AD 00 Address data B59 Vio I O supply A59 Vio I O supply B60 ACK64_N Acknlg64 from master A60 REQ64_N Request64 from master B61 5 V Supply A61 5 V Supply B62 5 V Supply A62 5 V Supply Table 12 Pin Assignment for PCI Interface Key Milling for PCI connector Copyright Siemens AG 2010 All rights reserved 31 EB 200 Manual Technical data ...

Page 32: ..._SEG0 Segment address0 A21 3 3 V Supply B22 M Ground A22 LBU_AB20 Address bus bit 20 B23 LBU_AB19 Address bus bit 19 A23 LBU_AB18 Address bus bit 18 B24 LBU_AB17 Address bus bit 17 A24 M Ground B25 3 3 V Supply A25 LBU_AB16 Address bus bit 16 B26 LBU_AB15 Address bus bit 15 A26 LBU_AB14 Address bus bit 14 B27 LBU_AB13 Address bus bit 13 A27 3 3 V Supply B28 M Ground A28 LBU_AB12 Address bus bit 12...

Page 33: ...8 LBU_DB01 1 bit data bus A58 LBU_DB00 0 bit data bus B59 Vio I O supply A59 Vio I O supply B60 Reserved A60 Reserved B61 5 V Supply A61 5 V Supply B62 5 V Supply A62 5 V Supply Table 13 Pin Assignment for LBU Interface Key Milling for PCI connector 7 3 External DC Power Supply In stand alone mode the EB 200 must be supplied with an external regulated 6 9 VDC 1 5 A power supply by means of a conne...

Page 34: ...ield collar M_EXT Shield permanently connected Table 15 Pin Assignment for Ethernet Switch Interface Downlink The LAN cable from to the evaluation boad must not be longer than 30m 7 5 Serial Asynchronous Interface The ERTEC 200 has one asynchronous serial interface The required pins are multiplexed as alternative GPIO pins The UART along with the RS232 interface driver is directly connected to a 9...

Page 35: ...PIO 16 GPIO 14 S GPIO 17 GPIO 15 S GPIO 18 M V Ground 19 BSCAN_EN_N S BSCAN_EN_N 20 M V Ground Table 17 Pin Assignment for GPIO 15 to 0 Connector name X21 Connector type 2x10 pin male connector Pin Signal Name Type Meaning 1 P3V V Supply 2 GPIO 16 S GPIO 3 GPIO 17 S GPIO 4 GPIO 18 S GPIO 5 GPIO 19 S GPIO 6 GPIO 20 S GPIO 7 GPIO 21 S GPIO 8 GPIO 22 S GPIO 9 GPIO 23 S GPIO 10 GPIO 24 S GPIO 11 GPIO ...

Page 36: ... Bit 1 buffered 4 B A 2 EMIF Address Bit 2 buffered 5 B A 3 EMIF Address Bit 3 buffered 6 B A 4 EMIF Address Bit 4 buffered 7 B A 5 EMIF Address Bit 5 buffered 8 B A 6 EMIF Address Bit 6 buffered 9 B A 7 EMIF Address Bit 7 buffered 10 B A 8 EMIF Address Bit 8 buffered 11 B A 9 EMIF Address Bit 9 buffered 12 B A 10 EMIF Address Bit 10 buffered 13 B A 11 EMIF Address Bit 11 buffered 14 B A 12 EMIF A...

Page 37: ...able 21 Pin Assignment for X31 EMIF Data Bits Connector name X32 Connector type 2x10 pin plug connectors Pin No Signal Name Function 1 P3V 3 3 V 2 B D 24 EMIF data bit 24 buffered 3 B D 25 EMIF data bit 25 buffered 4 B D 26 EMIF data bit 26 buffered 5 B D 27 EMIF data bit 27 buffered 6 B D 28 EMIF data bit 28 buffered 7 B D 29 EMIF data bit 29 buffered 8 B D 30 EMIF data bit 30 buffered 9 B D 31 E...

Page 38: ...6 19 TDI JTAG data in 20 TRACEPKT5 TRACE data bit 5 21 TRST_N JTAG Reset 22 TRACEPKT4 TRACE data bit 4 23 TRACEPKT15 TRACE data bit 15 M for test board 24 TRACEPKT3 TRACE data bit 3 25 TRACEPKT14 TRACE data bit 14 M for test board 26 TRACEPKT2 TRACE data bit 2 27 TRACEPKT13 TRACE data bit 13 M for test board 28 TRACEPKT1 TRACE data bit 1 29 TRACEPKT12 TRACE data bit 12 M for test board 30 TRACEPKT...

Page 39: ...nd 17 Not used DBREQ Default not used with test board 18 M Ground 19 Not used DBGACK Default not used with test board 20 M Ground Table 24 Pin Assignment of JTAG Interface 7 10 JTAG Programming Interface for FPGA Byte Blaster JTAG interface for interfacing of PCI FPGAs Connector name X62 Connector type 2x5 pin male connector Pin No Signal Name Function 1 TCK JTAG test clock 2 M Ground 3 TDO JTAG d...

Page 40: ...ups on the EB 200 o Selection of boot medium and boot software o Selection of the ERTEC 200 configuration o Activation deactivation of different board functions The exact position of the two connectors is shown schematically in Section 7 The following convention applies to all connectors 0 Jumper connected 1 Jumper not connected 8 1 Boot Configuration Connector X10 Connector X10 is used to specify...

Page 41: ...and configuration modes refer to Section 2 1 2 Connector name X11 Connector type 2x8 pin male connector Pin Signal Name Type Meaning 1 M 2 CONFIG 5 3 M 4 CONFIG 6 5 M 6 SPI_CONFIG 7 M 8 SYS_CONFIG 0 9 M 10 SYS_CONFIG 1 11 M 12 SYS_CONFIG 2 13 M 14 SYS_CONFIG 3 15 M 16 SYS_CONFIG 4 Table 28 Connector X11 for Configuration and System Settings Copyright Siemens AG 2010 All rights reserved 41 EB 200 M...

Page 42: ... is equipped with 4 holes onto which the supplied spacers are mounted 9 2 Front and Display Element external power supply 6 9V 1 5A RJ45 jack with LED s link and activity 2 LED s for board state signalisation e g RUN and SF Figure 6 Front Element of the EB 200 Copyright Siemens AG 2010 All rights reserved 42 EB 200 Manual Technical data subject to change Version 1 1 4 ...

Page 43: ...O 2 Red On Bus fault of ERTEC200 starter kit Sync GPIO 3 Green On ERTEC200 starter kit has been synchronized to the network clock Table 29 Function of LEDs on Front Panel of the EB 200 The display LEDs of the RJ45 sockets are directly connected to the LED outputs of the PHYs integrated in the ERTEC 200 Optionally these LED outputs can be converted to a GPIO alternative function In this way softwar...

Page 44: ... Input Output ICU Interrupt Controller Unit IP Intellectual Property IRQ Interrupt Request IRT Isochronous Real Time ITCM Instruction Tightly Coupled Memory JTAG Joint Test Action Group LBU Local Bus Unit NMI Non Maskable Interrupt PLL Phased Locked Loop PROFINET Field device connection via Ethernet SCRB System Control Register Block SDRAM Synchronous Dynamic RAM SPI Standard Serial Peripheral Int...

Page 45: ... Reference Manual ARM946E S REV1 16 February 2001 DDI 0201A_946ES PDF 5 Technical Reference Manual ARM946E S 16 December 1999 DDI_ 0165A_9E S_TRM PDF 6 Embedded Trace Macrocell Architecture Specification ETM_Spec PDF 7 Multi ICE System Design Consideration Applic Note 72 DAI0072A_Multiicedesign Notes PDF 8 IEEE Standard Test Access Port and Boundary Scan Architecture 1149 1 IEEE Boundary Scan 2001...

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