The bus enable assignment sequence begins with CPU 1 after the
Reset signal is removed by the power supply, and enables the CPUs in
the following order according to the preset number of CPUs:
CPU 1, CPU 2, CPU 3, CPU 4, CPU 1, CPU 2 etc. (see Figure 6-7)
Monitoring for continuous bus assignment
The bus lock signal can only be emitted by the CPU which has already
received a bus enable signal from the COR 923C. The bus enable time
is extended by the duration of the bus lock signal for the CPU (see
Figure 6-7). The factory setting for monitoring of the bus lock signal
is 2 ms. If the signal remains active for a longer duration, the
COR 923C emits a signal which results in a Stop of all CPUs.
The CPU which emitted the bus lock signal for too long a duration, is
marked by the CPU in a readable register under address FEFFH (fault
register, see Figure 6-8). The assigned BUS FAULT LED in the front
plate of the COR 923C lights up. The register is cleared and the LED
goes off again when the signal which led to the Stop state becomes
inactive.
CPUs in Operation
CPU 1
CPU 2
CPU 3
CPU 4
Bus Lock
Reset
Bus Enable for:
Time
Bus Lock
2us
2us +
Figure 6-7
Timing Sequences of the Bus Control Signals
923C Coordinator Module
System Manual
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C79000-B8576-C199-03
