Chapter 5
E300 Always-On (AON) Domain
The E300 platform supports an always-on (AON) domain that includes real-time counters, watch-
dog timers, backup registers, and reset and power-management circuitry for the rest of the system.
Figure 5.1 shows an overview of the AON block.
AON Power Source
The AON domain is continuously powered from an off-chip power source, either a regulated power
supply or a battery.
AON Clocking and Tilelink Slave Port
The AON block has a TileLink slave port to allow an external master to read and write registers
inside the AON block. The AON domain is clocked by the low-frequency clock,
lfclk
. The core
domain’s Tilelink peripheral bus uses the high-frequency
tlclk
. A HF-LF power-clock-domain
crossing (VCDC) bridges TileLink between the two power and clock domains.
AON Reset Unit
An AON reset is the widest reset on an E300 system, and resets all state except for the JTAG
debug interface.
An AON reset can be triggered by an on-chip power-on reset (POR) circuit when power is first
applied to the AON domain, an external active-low reset pin (
erst n
), or expiration of the watchdog
timer (
wdogrst
).
These sources provide a short initial reset pulse which is extended by the reset stretcher to provide
a shorter LFROSC reset signal
lfroscrst
and a longer stretched internal reset,
srst
.
The
lfroscrst
signal is used to initialize the ring oscillator in the LFROSC. This oscillator provides
lfclk
, which is used to clock the AON.
The
srst
strobe is passed to a reset synchronizer clocked by
lfclk
to generate
aonrst
, an
asychronous-onset/synchronous-release reset signal used to reset most of the AON block.
15
Summary of Contents for E300
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